The Design And Implentation Of SoC Full Automatic Test Platform Based On FPGA

Chips provide powerful hardware support for the development of information technology and artificial intelligence,and are widely used in intelligent life,transportation,medical care and other fields.So C chip is the development product of VLSI.From the design,manufacture,packaging and application,chip testing runs through the whole research and development process.The chip testing technology plays an important role in reducing the cost,shortening the development cycle and improving the flow rate.The test platform is composed of two functional parts.The part that can design the hardware and software of the test loop through the flexible programmable FPGA and processor is called the tester,and the part that realizes the multi-chip selection download through the communication between the microprocessor and the upper computer is called the downloader.The specific work completed is as follows:The burner and tester of the automatic test platform are based on EFM32G890 and Zynq 7020 chips respectively to design the peripheral auxiliary circuit to realize the chip burning and chip testing functions.The burning device is composed of the lower computer and the upper unit.The lower computer communicates with the upper computer through the USB free drive protocol,and the highest data transmission speed is 64KB/s.The ICP protocol realizes the chip download function and the SPI protocol realizes the offline data transmission function.The upper computer builds the interface application program framework on the Visual Studio platform through MFC technology,and realizes the interface program's functions of selecting two chips,online and offline states,downloading verification and one-key automatic downloading control.Burning function provides automatic control platform for the realization of chip testing.The tester is the core of the realization of chip function and performance testing.Zynq has the hardware architecture of FPGA equipped with core processor.In the part of programmable logic,the design of GPIO,UART,I2 C and TIMER test loop modules is completed by using custom IP and IP reuse technology.The core processor is integrated with IP through AXI protocol,on which the peripheral circuit is designed to build the hardware platform.Through hardware and software design,UART realizes five groups of standard baud rate values with a recognition range of 9600bps?115200bps,a maximum error range of 2bps,and automatic switching control test of baud rate.GPIO implements 52 IO pins to unify output,input and interrupt control tests.I2 C implements100Kbit/s and 400Kbit/s rate data communication,as well as master-slave mode switching control tests.Timer realizes the PWM switching control test of capture input and excitation output under the working frequency of 50 MHz.Finally,based on the test circuit built by the tester hardware,the paper writes test code and generates HEX file according to the module test points,and realizes the automatic control of the test module by means of software download through the burning device.The chip automation test platform designed by this topic has been tested for many times and basically completed the requirements of the design indicators,including the multi-chip selection download test through the upper computer control and the function test of some communication modules of the So C chip to be tested.At the same time,the use of testing tools reduced the planned workload from one week to less than one hour.By integrating the processor with IP,co-design of hardware and software,and communication control with the upper computer,the design idea has certain reference value for expanding the chip function and electrical parameter performance,so as to realize the full automation test of the chip.