A Digital/Analog Mixed Signal Chip Test System Based On FPGA

The digital-analog mixed-signal chip(ADC,DAC,PLL,etc.)occupies a very important position in the modern communication system.With the increasing bandwidth and increasing frequency demand of the communication system,the high-speed ADC / DAC also trend towards high speed Precision of the direction of development,which also put forward a higher testing demand on the chip,greatly increasing the technical difficulty.Because of the differences between the interface protocol and the level of the ADC/DAC chip,the chip requires static and dynamic performance testing,which is not easy to design a common test system.This article mainly discusses the test system for high-speed ADC chip test aspects of the design,for DAC,PLL and other chips its test module due to space constraints,this topic is not discussed.This paper introduces the hardware module of the test system,which is divided into test board and test board.The test board uses virtex-7 series FPGA as the main chip,and the based board and the testing board are connected with each other through FMC standard interface.Logic design is divided into high-speed data transmission module and Microblaze control module.The high-speed module is mainly responsible for data reception,format conversion and high-speed transceiver configuration module.Control module to FPGA embedded Microblaze soft core as the core,AXI4 bus as an embedded system bus architecture.Using vivado IP integrator tool to complete the control module logic platform design,and finally use xilinx API library functions to complete the driver layer design.The test system communicates with the PC through the network port,and the host computer software receives the data transmitted by the network port to complete the calculation of the various dynamic parameters and outputs the results.The test results of the test system when the sampling frequency is 125 MHz and the three groups of signals(10.1MHz,30.1Mhz,70.1Mhz)are input in diffrent frequencies4.2,the test system test results meet the error range specified in the data sheet.