Design Of Analog-to-Digital Converter Hard IP Core

A novel hard IP core of analog-to-digital converter is achieved, with the transistor level circuit and physical layout designed in detail.The IP core contains a Successive Approximation ADC and interface control circuit. To meet the demand of embedded application, some innovative cell circuits are introduced, which have been approved by the theoretic deduction and computer simulation.The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.To cancel the offset-voltage of the comparator, a switch capacitance circuit is used between the three pre-amplifier stages. The charge pump circuit is used to boost the clock voltage of the switch transistor.The DAC's output voltage can be exported by two groups of line-output structure. The simulation result shows this structure also can low the effect of the parasitic capacitances. A circuit is designed to define the odd and even line to meet the layout's simplification requirement.To make full use of the system resource, an auto-test circuit is designed with test vector can be given through the internal bus and result vector can be detect by system. The auto-test process could be done by several instructions' executed.Results of the IP core's simulation shows the ADC can achieve a 10-bit resolution. System has 8 input channel and 5 sample period selection with the control of internal bus. So the Analog-to-Digital Converter Hard IP core can be embedded in every type of micro-controller.