Research And Implementation Of High-speed Optical Receiver Front End And Clock And Data Recovery Circuits

Since the widespread deployment of optical communication systems in the 1980s,the global telecommunication capacity per capita and world data storage capacity per capita have doubled every 34 months and every 40 months,respectively.Driven by applications such as hyperscale data centers,cloud computing,the Internet of Things,and 5G communications,an-nual size of the global datasphere is expected to reach 175 Zettabytes by 2025;on the other hand,the portion within data centers still accounts for the vast majority of global data center IP traffic.Therefore,massive volume of frequently updated data in multiple formats raises higher demands for designing rack-to-rack and intra-rack optical interconnects covering transmission distances over 100 meters,where the transmission capacity is about to exceed the current 100-Gb/s standard.The challenges and trade-offs of designing high-speed optical interconnects,es-pecially the optical receiver front end?including linear equalizers?and clock and data recovery circuits,are investigated in depth.Accordingly,several new techniques and circuit structures are proposed and verified through the fabrication and measurements of three chips.The dependence of f_T,f_MAXand f_MINof SiGe HBTs on the biasing current density is analyzed theoretically and verified by simulation.A method for optimizing the biasing current of the transistor is proposed.In addition,the loss mechanism and lumped models of high-speed passive interconnects like inductors,transmission lines and capacitors are studied.A method for accurately extracting parasitic parameters of interconnects is introduced.Technical obstacles in the high-speed,high-gain and low-noise optical receiver front end design are discussed;and pros and cons of the existing structures are compared.Sepcifically,the comprehensive analytical expression of the input-referred noise current power spectral den-sity of the common-base shunt-feedback transimpedance amplifier is derived,which offers in-sights for noise optimization.Moreover,a modified variable-gain amplifier operating with au-tomatic gain control adaptively improves the linearity of post amplifying stages.Based on the research,a 56-Gb/s high-gain,low-noise optical front end in 0.13-m SiGe process is imple-mented.The proposed chip has been successfully tapped out and verified by on-wafer mea-surements,where the whole die area is 0.9×0.6 mm².The measured bandwidth of 31 GHz,the maximum transimpedance of 71 dB?,and the average input-referred noise current density of 14.54 pA/??? are achieved.The results demonstrate that the chip not only alleviates the dependence of bandwidth and stability on input capacitance,resulting in wide bandwidth and high transimpedance simultaneously,but shows the potential of a low noise level.The frequency response of the continuous-time linear equalizer,and adaptive equalization techniques are studied.By investigating the spectrum-balancing adaptive methodology based on high-and low-pass filtering and the power detection and error comparison techniques,a new adaptive circuit structure is proposed,which simplifies the adaptation loop and reduces the chip area and power consumption.Apart from that,techniques for improving power supply noise suppression through on-chip power management circuits consisting of a bandgap reference and a low dropout regulator are researched.Finally,a 10-Gb/s continuous-time linear adaptive equalizer with enhanced power supply noise rejection is fabricated in 0.13-m SiGe process.According to the post-layout simulation,the on-chip power management circuitry provides a significant improvement in power supply noise rejection of over 30 dB in 4-MHz bandwidth.The chip has been successfully tapped out and evaluated in a 12-pin QFP package,where the die area is 0.9×0.85 mm².The measured eye width after equalization is 0.6 UI,and the optical sensitivity of-30 dBm is achieved for the bit error rate less than 10^-3.The dependence of the stability factor and jitter tolerance of the 2nd-order and 3rd-order bang-bang loops on loop filter parameters is closely studied.Understanding the dependency is conducive for loop optimization.Furthermore,the design methodology of emitter-coupled logic and current-mode logic are elaborated.Additionally,methods for controlling the delay and minimizing the reflection in high-speed signal paths are investigated.Compared to conventional spiral inductors,the employment of RF lines in resonators of the VCO saves the area of the entire chip without sacrificing the performance.By studies above,a 25-Gb/s full-rate clock and data recovery chip that features ultra-low-jitter is proposed in 0.13-m SiGe process.The design is applicable to 100-Gb/s optical interconnects,wherein the topology is a 3rd-order type II bang-bang phase-locked loop.The loop parameters are determined in the light of detailed analysis and simulation of the stability factor and jitter tolerance.The core area of the chip is 0.48 mm².The measured results indicate that the chip recovers the clock with RMS jitter of 750 fs and peak-to-peak jitter of only 3.46 ps.