Digitally enhanced high resolution pipelined analog-to-digital conversion

CMOS Analog-to-digital converters (ADCs) are used extensively in modern electronic systems to take advantage of the benefits provided by processing signals digitally. Digital signal processing offers increased programmability, improved noise immunity, simplified automated design and testing, and improved cost and performance from the scaling properties of CMOS integrated-circuit (IC) technologies.; However, when analog functionality is replaced with digital, more stringent requirements are placed on ADCs because less analog pre-processing is performed on the ADC input signal and a larger portion of the IC contains “noisy” digital signals. Pipelined ADCs (PADCs), consisting of a cascade of low-resolution ADC stages, have become a popular ADC architecture due to their ability to achieve medium-to-high speed with medium-to-high resolution. However, performance is sensitive to the inevitable errors due to analog circuit imperfections present in each stage of the PADC, in particular interstage gain errors and digital-to-analog converter (DAC) element mismatches.; In this dissertation, the performance of PADCs is enhanced using digital signal-processing techniques that correct for inherent analog circuit imperfections. A gain-error correction (GEC) technique is introduced that continuously estimates and corrects for errors resulting from interstage gain errors. Chapter 1 presents a 1.8-V 15-bit 40 Msample/s CMOS PADC that achieves 90-dB SFDR and 72-dB peak SNR. The IC is the first silicon implementation of the GEC technique and a DAC noise cancellation (DNC) technique, which corrects for errors due to DAC element mismatches. Together these techniques result in a better than 20-dB improvement in SFDR and a better than 12-dB improvement in SNDR. The theoretical basis for the GEC technique is presented in Chapter 2.; An integral component of the DNC technique is a dynamic element matching (DEM) DAC that replaces the conventional DAC present in each stage of the PADC where DNC is used. The size of the digital encoder employed by the DEM DAC dictates the size of the digital logic required to implement the DNC technique, and is doubled with each additional bit of resolution. Chapter 3 addresses this problem by introducing segmented tree-structured dynamic element matching DACs that offer reduced DEM encoder complexity.