A Research And Design On Medium-speed High-resolution Successive Approximation Analog-to-digital Converter

The successive approximation analog-to-digital converter has been widely applied in wireless communication and data acquisition systems.In recent years,the SAR ADC is able to achieve competitive performance with lower power consumption,since it benefits much from advanced process node.Thus,the SAR ADC has become a hotspot in the ADC topic.At present,the research topic of low-resolution low-speed and ultralow power SAR ADC as well as that of high-speed and low-resolution SAR ADC has been well developed.While,SAR ADC of high-resolution is still very worthy of study.This dissertation will focus on the research of medium-speed and highresolution SAR ADC.The major contents include: the background of SAR ADC,basic theories of SAR ADC,architecture of SAR ADC,sub blocks of SAR ADC,digital calibration of SAR ADC and the simulation of SAR ADC.In this design,bottom-plate sampling technique is applied to eliminate the side effects of charge injection and clock feedthrough for high-resolution sampling.And the CDAC is designed to be splited,which reduces the amount of unit capacitors and increases the unit capacitance.This is desirable in high-resolution SAR ADC design.This dissertation proposed an innovative internal clock generator,which adjusts the delay smartly and improves time efficiency.Also,a new SAR controller is implemented in this design and it achieves a much shorter critical path compared to a conventional one.A comparator with preamplifier and auto-zeroing technique is chosen to achieve low DC offset and low noise in this dissertation.Also,calibration techniques are studied,summarized and implemented by MATLAB codes and Verilog codes in this work.The simulation results show that the SFDR of the SAR ADC is 98.5 d B and the SNDR is 85.3 dB.