Enabling techniques for high-resolution analog-to-digital conversion in IC fabrication processes optimized for digital circuits

Advances in CMOS integrated circuit (IC) fabrication technology have made it possible to use digital signal processing techniques to realize many signal processing functions traditionally implemented with analog circuits. In communication systems, digital filters provide well-controlled frequency responses that do not depend on the matching of circuit elements. In audio signal processing systems, digitally-controlled gain and attenuation circuits can control signal levels without “clicks” and “pops” due to dc offsets in analog implementations. In addition, digital hardware is well-suited to the application of adaptive signal processing techniques.; Exploiting these benefits to provide a highly-integrated, single-chip solution requires analog-to-digital converters (ADCs) which can be integrated on a single chip in a CMOS fabrication process optimized for digital circuits. Current digital-optimized CMOS processes are typically limited to supply voltages below 3.3 V and lack high-quality passive components such as thin-oxide linear capacitors. As a result, designing analog circuits to achieve 16-bit resolution at conversion rates of 48 kS/s to 200 kS/s in such a process is a challenging task.; This dissertation presents signal processing techniques developed to enable the implementation of high-resolution analog-to-digital converters in digital-optimized CMOS fabrication processes. These techniques are implemented in digital circuitry and significantly ease the design of the analog circuits in the ADC. Chapter 1 presents a prototype audio-rate multibit ADC ΔΣ modulator using a 33-level first-order mismatch-shaping DAC which achieves 98-dB peak signal-to-noise-and-distortion (SINAD) and 105-dB spurious-free-dynamic-range (SFDR). Chapter 2 presents a prototype audio-rate multibit ADC ΔΣ modulator using a low-complexity 33-level second-order mismatch-shaping DAC which achieves 100-dB peak SINAD and 103-dB dynamic range. Chapter 3 presents the implementation and theoretical details of a dynamic element matching technique used in the prototype ΔΣ modulators to provide spectral whitening of comparator offset errors in the 33-level flash ADC quantizer. Chapter 4 presents the implementation and theoretical details of a digital common-mode rejection flash ADC used to provide differential quantization of the differential output of the switched-capacitor loop filter.