A new ATPG algorithm to generate compact test sets which detect static and dynamic defects in VLSI circuits

Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduce the overall defective part level. However, multiple observations of each fault site lead to increased test set size and require more tester memory. In this research, I propose a new ATPG algorithm to find a near-minimal test pattern set that detects faults multiple times and achieves excellent defective part level. This greedy approach uses 3-value fault simulation to estimate the potential value of each vector candidate at each stage of ATPG. The algorithm is applied to static defect testing as well as dynamic defect testing to handle timing errors in the circuit. The result shows that generation of a close to minimal vector set is possible only using dynamic compaction techniques in most cases and the defect coverage of the new test set is superior to test sets produced by a conventional approach. Finally, a systematic method to trade-off between defective part level and test set size is also presented.