Research On High-level Test Generation Algorithm For VLSI

Thanks to the rapid development of Integrated Circuits, the need for large-scale circuit design and reuse makes the design level have turned to the high level. Now most of the designs are carried out in register transfer level. The demand of reliability for electronic production grows day by day. The fully test on IC is wanted for digital system's working normally. At the same time, the relationship between the design for VLSI and the CAD tools is closer. All of these bring the challenge to the traditional gate-level test. The test generation is one of the key problems in test.Based on the techniques of the design verification or validation and test,for the high-level circuit models proposed up to now, the controllability and the observability can not behave to band together very well.The dissertation targets the problem for commonly used Register Transfer Level behavioral descriptions and proposes a circuit model-CRG model, which turn the circuits described by verilog HDL into the condition-results graph. This model can clearly incarnates the controlling and the data relationship,as well as the sequential information.At the same time, it's unimportant for us to understand the function of the circuits,for the model is extracted straightly from the statements of the program. A simulation-based algorithm is presented to generate for the activation and the observability of the statements. Simulation begins without specifying the inputs in advance. After some time's simulation, the partially fixed input sequence is then the generated test sequence. At last, we can finished them by filling up some stochastic bit instead of unspecified bit. The generated test sequence is for both design validation and functional test.We have carried out the experimentation on ITC99 benchmarks: Firstly,we get the test sequences based on our algorithm;Secondly, we put the test sequences on the circuits we selected via the software Modelsim6.0 from Mentor Graphics. The results show that the circuit model and the test generation algorithm are not only effective for generating test sequence but also can help for the testability analyse.