Research On ATPG Based On Test Vectors Applied By Circuit-under-Test Itself

Recently, Integrated Circuit(IC) developed to the field of deep-submicron, even nanometer, its function becomes more complicated and the integrated density increased quickly. On the one hand, it brings convenience life to human beings; on the other hand, complicated structure and high-speed system clock also make the testing more difficult.Owing to the traditional method cannot cope with the development of IC, then the Design-for-Testability(DFT) appeared, namely sufficient consideration of the test requirement when designing the circuit, so as to it can be easily tested.Scan-Path-Test(SPT),Boundary-Scan-Test (BST) and Build-in-Self-Test (BIST) are the most popular DFT technologies. On the other hand, because of the complication of testing, Genetic Algorithm (GA) has been applied to this field as a mature optimized algorithm, and solves a lot of problems.On the basis of introducing the principle of digital circuit testing and GA, we expound the basic idea of BIST technology, especially the hybrid BIST technology which combined with LFSR (Linear Feedback Shift Rigister) and storage TPG (Test Pattern Generator). And then we present a Automatic test generate method using Test Vectors applied by Circuit-under-Test(CUT) Automatically to solve some problems this traditional methods. In this method, CUT is not only regarded as the test object, but also a sort of available resource. The method captures the response from a part of interior node of the CUT by some capture registers, then feedback to primary inputs as the next test vector. Through the self-feedback structure, we can get a whole test set after the first test vector had been applied to CUT, it effectively decreased the storage cost of test vectors.In this paper, we use the C17 circuit as a sample to introduce the basic idea and implementation of this method in detail. Then we present a feasible test generation algorithm base on GA to find the best feedback combination. Some effective measures such as test set hamming distance and node offset have been used to accelerate the test generation process. The experimental results on the ISCAS85 benchmark circuits demonstrate that this algorithm can find an approximately optimal feedback combination in short time, and the test set generated by the feedback combination can reach high fault coverage under a short vector length.This paper also presented several methods, such as non-subsection reseeding,subsection reseeding and re-exchange feedback combination, to improved the problem that pseudorandom vector's fault coverage shortage, and some related experiment has been made. Finally, we proposed a method to test circuit using the vectors applied by CUT itself and a subset of MinTest according to the hybrid BIST which combined with LFSR and storage TPG. The experiment results shows that this method not only can achieve the same fault coverage, but also has an average 16.4% and 33.26% decrease in test vector length and ROM overhead compared with the hybrid BIST which combined with LFSR and storage TPG.