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Test Generation Based On Behavioral Model At RT-level And Delay Testing

Posted on:2002-04-03Degree:DoctorType:Dissertation
Country:ChinaCandidate:H W LiFull Text:PDF
GTID:1118360185495631Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Integrated circuit (IC) testing is a very important technique to guarantee the reliability of a digital system. As the semiconductor technology keeps moving towards the creation of monster chips, the growing complexity of modern ICs is driving the trend of test pattern generation (TPG) towards testing at high level, particularly at register transfer level (RT-level or RTL). At the same time, it is also more critical to perform delay testing to ensure correct temporal behavior of fast digital systems than before. This dissertation concentrates on TPG based on behavioral model at RT-level and delay testing techniques. It first surveys the recent development of test generation and delay testing techniques. Then, a new level of description on behavioral model is introduced, which is extracted from a behavioral description at RT-level. Techniques of test generation based on the new level of description are proposed. This dissertation also introduces a novel method of delay testing with variable double observations presented by the author, after summarizing the main methods of delay testing systematically. And a new approach to delay fault diagnosis based on the method is proposed. These techniques are adopted in two systems. One is a TPG system using clustering of circuit states, which implements automatic TPG based on behavioral model at RT-level. The other is a delay testing system based on variable double observations, including a TPG tool and a fault diagnosis tool.The original ideas in this dissertation are explained in detail.1. A new level of description between behavioral and low-level descriptions of Finite-State Machines is presented, termed behavioral phase clustering description. This description maps states of an FSM to behavioral phases at RT level. Clustering of behavioral phases is performed to represent the function of a circuit more explicitly and refinedly. Behavioral phase clustering descriptions bridge the high and low level descriptions. It can be used in functional analysis, verification and test of designs.2. A new fault model based on behavioral phase clustering description is...
Keywords/Search Tags:Register Transfer Level (RTL), Finite State Machine (FSM), Automatic Test Pattern Generation (ATPG), Delay Testing, Fault Diagnosis
PDF Full Text Request
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