Research And Implementation Of Low Power DFT Based On Scan Chain And ATPG

With the continuous progress of semiconductor manufacturing processes,and the increasing in the complexity of the circuit,the numbers of transistors per unit area and the frequency of operating,the issue of power during normal operation is no longer the only important focus in the field of integrated circuit power research,and the power during testing has become an issue that must be more and more considered.Because most of the logic circuits are usually evoked at the same time,the test power of the integrated circuit,especially for the peak power,will be much bigger than the normal operation power,which will cause many issues in terms of stability,reliability,test quality and manufacturing cost.Therefore,how to achieve low power test during the design and manufacturing stages of integrated circuits is becoming an increasingly important issue.Scan structure can improve the controllability and observability of internal nodes of the circuit during the test,which is widely used for its structured feasibility design method.In view of the above situation,the dissertation firstly discusses the various power,scan cells,scan chain,automatic test pattern generation,test pattern and so on in scan test.Secondly,from the perspective of scan chain and ATPG,the schemes with low power optimization are proposed for the scanning shift process and the scanning capture process,especially for the peak power.Finally,an IP core was used to create the corresponding circuits.Primetime PX power analysis tool was used to build a power simulation environment,and the proposed power optimization scheme was implemented,simulated,debugged and analyzed.The main work and innovations are as follows:(1)Aiming at the problem that during the scan shift process,a large number of nodes in the scan unit and logic circuits are flipped,as well as the duration is long,which causes the shift power to account for a considerable proportion of the total test power,the dissertation proposes a low power optimization method.In the scan test process,the inserted scan chain itself needs to be tested first.The scan chain usually runs through all the modules.And the test process will generate large test power.When an IP core is divided into multiple modules,by adding a shifting clock control block to each module and testing the module in a time-sharing manner,the dissertation optimizes the peak power by about 21.74% after solving the problems of simulation mismatch caused by the changes in the circuit structure,and the average power is also reduced.In the process of testing for functional circuits,in order to reduce the numbers of circuit units that are simultaneously flipped during the shift process,the dissertation proposes a method of peak shift test and the optimization of test patterns by EDT circuits as well.Through the peak shift test,the peak power was optimized by 15.60%.By assigning fixed values to the irrelevant bits and optimizing the test pattern,the peak power reaches about 17.88% optimization.(2)When the scale of the integrated circuit is large,the capture process will also generate large test power.The dissertation proposes a time-sharing capture scheme for different circuits testing in the internal modules of the IP core.For different sources of the capture clock,by configuring different test pattern generation environments,the peak power of the capture process was optimized by 12.20%.For capturing the test response under single clock control,the dissertation proposes a method of test pattern control and screening pattern with the help of EDT circuit.By generating test patterns with the clock gating unit and screening test pattern with the EDA tool,the peak power during the capture process an be optimized up to 79.13%.This optimization effect is closely related to the circuit structure.(3)Comparing the power data before and after optimization,the dissertation discusses the advantages and disadvantage of each scheme in combination with the number of test patterns,test coverage,the scanning unit structure and the circuit structure in the IP core.The optimization schemes proposed in this dissertation have great practicality and scalability,which can optimize the power,especially for the peak power,to a certain extent during scan shift and capture in the chip test process.