Research And Implementation Of Test Generation Based On IP Core Test

With the development of technology and the design of semiconductor chip design, raising the level of the system into a chip, using pre-designed standard IP module to construct the SOC chip method of system design gradually become the mainstream. Such large scale integrated circuit and the large scale of the embedded IP core, the failure of nuclear also will increase, this system to test chip put forward higher request. One need more accurate timing control, on the other hand, need to spend more time, this test chip leads to improve test cost. The use of SOC chip internal IP core, IP use, authorize, protection restrictions will bring more challenges for testing, in the SOC test be reuse IP restrictions IC design development bottleneck.Based on thorough study to test generation digital system theory and test data compression techniques, ISCAS with 85 and 89 series circuit C6288 and S344 etc for IP core test generation algorithm, using PODEM algorithm to get C6288 test vectors, using Golomb algorithm to compression coding for C6288 test vectors compression test yards after get compression. Based on this, advances P1500 IEEE standard test based on the design theory basis for the shell, Core test by IP information to the conversion of SOC test information "vector map" algorithm, we get the SOC of effective testing, testing and ISCAS89 vector of the benchmark circuits S344 circuit for the detailed story. Finally realized based on FPGA technology platform and simulation test model, through the design of the main controller TAP logic control, C6288 test and response to compress the data validation.Simulation and practical test results show that the metrology is feasible.The performance of the test system meets with requirements of SOC test.The test system illustrated in the dissertation has a prospective future in the applications.