Reducing digital test volume using test point insertion

Test cost accounts for more than 40% of the entire cost for making a chip. This figure is expected to grow even higher in the future. Two major factors that determine test cost are (a) test volume and (b) test application time. Several techniques such as compaction and compression have been proposed in the past to keep the test cost under an acceptable limit. However, due to the ever increasing size of today's digital very large scale integrated circuits, all prior known test cost reduction techniques are unable to keep the test cost under control.;In this dissertation, we present a new test point insertion (TPI) technique for regular cell-based application specific integrated chips (ASICs) and structured ASIC designs. The proposed technique can drastically reduce the test volume, the test application time and the test generation time. The TPI scheme facilitates the compression and the compaction algorithm to reduce test volume and test application time. By facilitating the automatic test pattern generation (ATPG) algorithm, we also reduce the test generation time. Test points are inserted using timing information, so they do not degrade performance. We present novel gain functions that quantify the reduction in test volume and ATPG time due to TPI and are used as heuristics to guide the selection of signal lines for inserting test points. We, then, show how test point insertion can be used to enhance the performance of a broadcast scan-based compressor. To further improve its performance, we use a new scan chain re-ordering algorithm to break the correlation that exists among different signal lines in the circuit due to a particular scan chain order. Experiments conducted with ISCAS '89, ITC '99, and few industrial benchmarks clearly demonstrate the effectiveness and scalability of the proposed technique. By using very little extra hardware for implementing test points and very little extra run time for the TPI step, we show that the test volume and test application can be reduced by up to 64.5% and test generation time can be reduced by up to 63.1% for structured ASIC designs. For the cell-based ASICs with broadcast scan compressors, experiments indicate that the proposed technique improves the compression by up to 46.6% and also reduces the overall ATPG CPU time by up to 49.3%.