| Continuous scaling down of CMOS device sizes and an accompanied increase in device switching speeds prompts the design of mixed-signal systems with increasingly complex digital signal processing and control algorithms accompanied by simpler analog circuitry. Analog to digital converter (ADC) is an essential mixed-signal component of modern receivers, where signals sensed from the source are converted to digital for further signal processing on them.; Deep submicron CMOS processes are characterized by high transition frequencies fT and increased channel length modulation. In terms of analog amplifiers this translates to a high bandwidth but low DC gain. This in turn means that monolithic ADCs, which rely largely on switching circuits, capacitors and operational transconductance amplifiers (OTAs), can be designed with high sampling rates but cannot meet high resolution requirements (without the use of techniques like noise-shaping).; In this dissertation, calibration techniques are presented which allow ADCs to be designed with large inherent gain and offset errors. The concept of arbitrary radix multistep conversion is presented, along with algorithms that enable reduced radix conversion with digital correction in pipelined or algorithmic ADCs. Calibration techniques that account for linear and nonlinear gain error are presented and adapted to the popular 1.5 bit/stage pipeline architecture. Calibration is performed purely with digital post-processing on ADC output bits, with no changes occurring in the analog hardware.; Background calibration is essential for applications where time-varying gain errors require continuous correction, which must be transparent to the user or client system using the ADC. Techniques that enable background calibration are presented, and a novel queue architecture is shown which allows pipelined ADCs to be background calibrated without the addition of any additional analog hardware. Due to the identical design of all calibrated stages, a pipelined ADC also becomes suitable to reconfiguration that allows power consumption to be scaled linearly with the required conversion speed and accuracy.; In this dissertation a WCDMA/WLAN receiver architecture is presented and specifications are derived for all its components. Concept of reconfigurable ADC design is presented, which allows speed and power consumption optimization. (Abstract shortened by UMI.)... |
