Research And Design On The Key Techniques Of High Speed Pipeline ADC

With the fast development of the wireless communication,5G wireless networks will achieve peak data rates up to lOGbit/s,it requires Multi-GS/s high speed ADC,and the requirements of resolution,chip area and power consumption are becoming more stringent.Compare to other ADCs,Pipeline ADC and Folding and Interpolating(F&I)ADC can realize high conversion rate by one channel.Therefore,the research of high speed ADC based on Pipeline and F&I have a great significance.The Pipeline ADC and F&I ADC with single channel is studied in detail.The key techniques for further reducing the power consumption and improving the conversion speed of the two style ADCs are discussed in depth.The main research contents of this thesis are follows:(1)This dissertation analyses the basic principle and redundant digital correction of Pipeline ADC,the main error sources,modular circuits are explored deeply.The settling performance of MDAC and the effect of switch resistance on the settling time are analyzed in detail.The design method of high speed pipeline ADC and its subcircuits based on deep sub-micron CMOS technology are researched deeply.A symmetrical bootstrapped switch was proposed,which adopts novel circuit structure to suppress charge injection and body effect,reduce the gate parasitic capacitance of the MOS.A high speed and low kickback noise comparator was proposed,the kickback noise is caused by the voltage variations on the nodes that are coupled to the input.Cross-coupling capacitors are added to the input of the pre-amplifier to reduce the kickback noise.The kickback noise is reduced from 1.5mV to 0.5mV.A high speed 12bit 500MS/s Pipeline ADC with the proposed circuit techniques is realized in 65nm CMOS technology.The simulation results show that the sampling rate of this ADC is up to 800MS/s,the power consumption is 225m W from a 1.2 V supply.(2)The sampling and holding circuit with input buffer is studied carefully,the super-source follower and its linearization method is studied thoroughly.On the basis of above research,a high speed and high linearity sampling and holding circuit with input buffer was designed in 65nm CMOS technology.The circuit uses two feedback loops to reduce the output impedance and improve linearity.It consumes only 27mW from a 1.2V supply.Simulation results show that 12.6 bit linearity was achieved with a 1.5GS/s input signal.(3)In order to further improve conversion rate and reduce the power consumption,a novel loading-balanced system architecture is presented in this dissertation.It uses Op-amp and capacitor sharing technique,Op-amp and capacitor scaling down technique,SHA-Less and non-standard inter-stage gain to realize loading balance of the op-amp shared by the first two stages.The proposed architecture increases the conversion rate and improves the total performance of the Pipeline ADC.The memory effect of the shared op-amp and capacitor was analyzed,and the solution was provided.And then a high speed 12bit 500MS/s Pipeline ADC is designed in a standard 65nm CMOS technology using the proposed architecture,the total power consumption of the prototype is only 147mW with a 1.2V supply voltage.(4)In high speed F&I ADC design,an important issue is the encoding error result from the fine and coarse channel joint encoding technology.The sixth bit of the ADC only uses the last comparator of the fine channel to encode,the misjudgment of this comparator caused by offset and other non-ideal factors will lead to the encoding error of the sixth bit.A digital encoding calibrated unit is presented in this paper.An 8bit 1GS/s high speed F&I ADC with this encoding calibrated unit is fabricated in 0.18μm CMOS technology with this digital encoding calibrated unit.The measurement results assess the validity of the calibration.