Research And Design Of High-performance Clock Driver Circuit

As sampling speeds increase, it becomes more and more important to be able to generate high performance clock. The clock signal should be low-jitter and of which the duty cycle and crossing-point need to be controllable. These demands are more and more critical in double data rate (DDR) systems, including the DDR-SDRAM, Timing-interleaved ADC, differential-quad switching DAC, etc. Traditionally, clock driver designers only considered the duty cycle of clock signals and the driver capability, but the influence of noise and the position of the crossing-points are being felt. This work covers the driver capability, clock jitter, duty cycle, and the position of the crossing-points. And this work shows how to enhance the driver capability and improve the quality of the clock signal.Based on the requirement of the whole system, the clock driver is divided into six circuit modules, including the low noise operational amplifier, duty cycle detector, duty cycle corrector, crossing-point detector, crossing-point corrector, and the inverter chain. Detail analysis has been done for every circuit module. For example, because the clock driver is a non-linear system, this work provides detail analysis on how the noise spectrum characters change in the non-linear system, and points out the source of noise in different band. Although there are two feedback loops in our clock driver design, they are irrelevant, which simplifies the design process.Circuit of clock driver was done using TSMC 0.18um technology. For a system running at 1GHz and driven with a 6% duty cycle error input (0.6Vpp), the jitter is about 35fs and the duty cycle of the output is improved to 49.94%. In addition, the crossing-point is adjustable between 81mV～1.3V.