| High-speed CMOS serial links have been crucial in matching off-chip system bandwidth with the increasing on-chip demand. Conventional serial link architectures typically use multi-phase clocking structures to achieve a pin bandwidth faster than the on-die logic switching speed. However, such multi-phase clocking architectures typically use several stages of clock fanout buffering, which dissipate considerable power and suffer from significant sources of timing uncertainty, namely power supply induced jitter and process dependent static phase offset.; This thesis presents a new serial link architecture which addresses the timing uncertainties caused by power supply noise and process mismatch. First, process variation and power supply sensitivity in serial link clock buffers are examined and then shown to de grade further in future scaled CMOS processes. Next, a new architecture is presented that alleviates this problem: direct drive resonant clocking. The complementary phases of an integrated LC-VCO directly drive the final output multiplexer in the transmitter, resonating the capacitive load and eliminating clock buffers, thereby reducing power dissipation, power supply induced jitter, and static phase offset. In the receiver, a similar technique is applied, where the front-end 10GHz input sampler is directly driven by a different LC-VCO. Several side-effects of this direct drive resonant clocking technique such as increased kickback-induced jitter, reduced tuning range, and reduced bandwidth are examined. Finally, two test chips are designed and fabricated in 0.13um CMOS technology, exhibiting a 20Gb/s data rate, low power(165mW in the transmitter), and low area. The resulting power supply susceptibility is reduced by 10x and process mismatch phase error by 5x. |
