Research Of CMOS Inductorless Wide-Band Frequency Synthesizer

Modern system on chip(SoC)usually has multiple clock generators to drive its building blocks.The most common solution for clock generation is phase locked loop(PLL)based frequency synthesizer.The clock jitter performance of the periodical sig-nal determines the establishing time and working frequency of digital systems.It is usually required that a PLL should achieve low phase noise and low power under com-plex environments.In order to meet these requirements,it is essential to design a high performance oscillators.L-C tank oscillator is widely used due to its superior phase noise performance.The noise performance of ring oscillator is not comparable to L-C counterpart,but its area-effeciency and wide tuning range will lower the cost of chip fabrication which is important for SoCs.Most ring oscillators are tuned by current to expand their tuning range.This will lead to a large offset of DC bias under some extreme conditions,causing a performance degeneration.The large and nonlinear tuning gain of oscillator will also give rise to stability issues to PLL and magnify spurious tones and noise coupled to the control voltage.The phase noise and frequency tuning issues of CMOS ring oscillator are an-alyzed and a differential ring oscillator with linearized and split tuning is presented.The proposed tuning technique applies a V-I convertor and MOS load arrays to realize wide tuning range without compromising noise performance at lower frequency.The proposed oscillator is fabricated in a 180nm CMOS technology.Measurements show that the oscillator has reached a phase noise of-93.5 dBc/Hz at 1MHz offset of 1.4GHz with a power consumption of 2.9mW,drawing an FoM2 of 151.8 dBC/Hz.Apart from the inferior noise performance,ring oscillators are also sensitive to process,temperature and supply voltage variations.The current pulses generated by the switching operations of digital circuits will couple through the substrate and be-come supply noise,which is a major performance limit to ring oscillators.In order to alleviate the impact of supply noise,voltage regulators are often employed.However,the regulators will bring extra power consumption and stability issues to PLL.This pa-per introduced an open loop compensation technique that reduce the supply sensitivity of ring oscillators by controlling tail current sources.The proposed circuits are fabri-cated in 180 nm CMOS process and the effectiveness of supply rejection is proved by measurement results.The building blocks of an SoC usually have different requirements for clock sig-nals.Due to economic considerations,a universal clock generator IP is often used in-stead of designing individually for each block.This paper introduced a low power,low area frequency synthesizer IP on 40 nm CMOS technology.Multi-oscillator structure and automatic frequency calibration is employed to cover a frequency range from 100 MHz to 3.2 GHz.A dynamically matched charge pump and capacitance multiplication is applied to lower the chip area and in-band noise.Post-layout simulations indicate that the proposed PLL realized an rms jitter of 3.1 ps at 3.2 GHz with a power consumption of 5.05 mW and chip area of 0.045mm2.