Study And Design Of Low Jitter Frequency Synthesizer Based On Ring Oscillator

With the development of communication technology and semiconductor technology,the operating frequency of key circuits such as analog-to-digital converters and serial interfaces in the system-on-chip has become higher,which puts forward higher requirements on the jitter and integration of the clock source.Frequency synthesizers based on phase-locked loop is widely used due to its advantages of high output frequency and simple structure.The realization of high integration and low jitter characteristics is its research focus.Based on 65 nm CMOS process,a frequency synthesizer with low jitter characteristics is studied in this thesis.A sub-sampling phase-locked loop structure is used to achieve better jitter performance.Establish a linear model of the system,and derive the noise transmission characteristics of modules such as voltage-controlled oscillators and phase detectors.Based on matlab to verify system functions,optimize loop parameters and calculate phase noise.In order to achieve higher integration,the voltage-controlled oscillator adopts a ring structure,and a differential structure delay unit is proposed based on the feedforward theory and the Hajimiri phase noise model.The realized ring oscillator has low phase noise.To achieve low jitter,the sub-sampling phase detector-charge pump and the modules in the frequencylocked loop are designed.With full consideration of various non-ideal factors,technologies such as controllable delay units,complementary switches,and operational amplifier clamps are used in the actual circuit to reduce the impact of non-ideal effects on system performance.The noise simulation results of each module are substituted into the loop model,and the loop parameters are adjusted according to the phase noise curve to design the loop filter.Finally,the designed low-jitter frequency synthesizer is simulated and verified.The overall simulation results of the system show that the loop lock time at each output frequency is less than 5?s at the input reference frequency of 26 MHz.When the output frequency is 1.248 GHz,the loop lock time is 3?s,and the overall power consumption is8.64 m W.The phase noise of the ring oscillator is-106.7d Bc/Hz@1MHz,The overall phase noise of the loop is-115.4d Bc/Hz@10KHz,The mean square value of jitter in the integration area [10KHz 100MHz] is 0.87 ps,The reference spur is-54.4d Bc,which achieves good jitter performance under certain power consumption.