The Research Of Current Efficiency For LC Oscillator And Design For Ring Oscillator In CMOS Process

CMOS oscillators, responsible for frequency generation and clock reference, are the common and essential components of modern communication systems. CMOS oscillators are mainly classified as LC oscillators and ring oscillators. LC oscillators have superior phase noise performance and they can be applied to high frequency. Meanwhile, ring oscillators have advantages of occupying small chip area and wide tuning range. LC oscillators and ring oscillators can be used as a part of phase-locked loop (PLL) in different parameter requirement systems.High spectral purity and low power consumption are the key point and difficult problems to design an oscillator with good performance. Current efficiency, because of its close relationship to spectral purity and power consumption, has become a popular direction of oscillator research in recent years. Quantitative analysis is shown in this paper to analyse the current efficiency of class-B and class-C LC oscillators, which are widely used in industry field. The expressions state the relation among boundary angle, conduction angle and current efficiency ?1. The errors between simulation results and theoretical expressions are within 0.05. Furthermore, current efficiency can not only be used to deduce the expression for phase noise in 1/f2 region of oscillators with high amplitudes but also can be used to design oscillators with high FoM.Radio frequency identification (RFID) technology, as it can deal with large information in a short time without direct contact, can improve the accuracy and timeliness of information. Phase-locked loop, is the key circuit responsible for RFID reader chips'performance, which provides local oscillation frequency for RFID reader chips and voltage controlled oscillator is the main difficulty and key point to design a PLL. Post simulation results showed that the proposed PLL had an output frequency ranging from 840-960 MHz and a 31.21mW power consumption. Its phase noise was-108.5dBc/Hz at 100 KHz offset at 840.125MHz and -132.3dBc/Hz at 1MHz. By comparison with other PLLs, the proposed PLL has advantages in the consumption and phase noise.Owing to their inductorless, occupying small chip size and wide tuning range, ring oscillators are widely used in low and middle frequency communication systems. This paper shows two applications of ring oscillators. The first one is used in a 1.5-3 GHz charge pump PLL with a practical output frequency ranging from 1.13-3.73 GHz. Its phase noise was -60.49dBc/Hz at 100KHz and -86.84dBc/Hz at 1MHz offset. The other one is an open loop compensation technique for reducing supply sensitivity of ring oscillators. A current bias circuitry of negative supply sensitivity is applied to compensate the frequency variation caused by supply noise. The simulation result showed that the supply sensitivity of ring oscillator is reduced to 0.0095 mUI/mV. The ring oscillator achieves a phase noise of -96.5dBc/Hz at 1MHz offset with an overall power consumption of 1.7mW.