Research On The ESD Protection Devices And Applications In Co-design With Circuits

With process featured-size shrinking and integration scale increasing continusly,electrostatic discharge(ESD)of IC(Integrated Circuit,IC)is becoming more and more significant.The influence of electrostatic discharge caused by walking on the ground of can be extremely dangerous for electronic products.Except the electrostatic discharge impact,adsorption impurities due to electrostatic may also be in a clean environment or the product adhesion together.Starting in the 1970 s,ESD damage in electronic products,especially the human body electrostatic discharge thread caused a large number of product failure and yield decreased.From then on,the industry made efforts to reduce the ESD damage in electronic devices from the aspects of device structure optimization,circuit design,process control and application,and then ESD protection technology have become the research focus in the IC industry.This dissertation focuses on the design techniques of ESD protection for integrated circuits,including ESD protection devices optimized design,the whole chip ESD protection and ESD protection co-design techniques related with system in package(SiP).The discussions about ESD protection are carried out on different levels from basic devices,circuits design to system in package modules design.The main contents of this paper are summarized as follows:(1)Based on prior solutions to optimize the design of ESD protection device silicon controlled rectifier(SCR),the holding voltage will be increased to improve the immunity of the latch-up effect.An improved cathode and anode layout optimization method with fully segmention is proposed.By reducing emitter injection efficiency and layout optimization,the holding voltage and failure current capability are trade-offed,keeping relatively high failure current density in dual-directional SCR.Meanwhile,two kinds of different fully segmentation SCR(SeSCR and Anti-SeSCR)are discussed.By changing the current flow path,the changes the overall intrinsic in the SCR device and the intrinsic diode current distribution situation lead to different behaviors under ESD stresses.The performance of SeSCR and Anti-SeSCR can be adjusted to satisfy different application requirements of ESD protection features with the different ratio of segmentation,segmentation width and layout topologies.(2)Adding the bypass current path to reduce the proportion of the emitter current in the SCR also can increase the holding voltage of SCR.In this dissertation,a method of external emitter parallel resistance is studied.The holding voltage increases with the decrease of the shunt resistance,which proves the flexibility and validation.For SCR emitter current in the current path,the holding voltage can affected by adding additional transistor to shunt its proportion with inserting compensation layers in the dual-directional SCR,leading to higher holding voltage.The simulation analysis and measurement results reveal the effectiveness of this method.(3)The design of whole chip ESD protection is essential for IC products.By analyzing the device structure in bipolar process,a general-purpose operational amplifier with the ESD protection design is realized.Especially,the output stage holds the self-protection capability with the parasitic characteristics of devices,and the whole chip human body model(HBM)ESD protection capability is more than 4k V.According to the characteristics of the CMOS process and the structure of video multiplex amplifier,the whole chip ESD protection is implemented based on the power rail optimization design.The whole chip HBM ESD protection ability is elevated from 600 V to 3.5kV through optimizing the power rail between the clamping structures,fulfilling the requirements of industrial applications.The above analysis adopts transmission line pulse(TLP)method to evaluate the characteristics of ports and find out the weak failure spots of the chips.Finally,the ESD performance of the circuits are improved.(4)On the basis of ESD protection design techniques of components and chips,the co-desgin ESD protection techniques with on-chip and on-board devices are analyzed with experimental cases.With the analysis of characteristics of on-chip ESD protection structures,the optimized on-board protection strategies are proposed to improve the ESD capability of the thin film resistors in a mixed signal Si P and differential signal ports in RS422/485 interface chips.The trade-off among aspects including reliability,cost and time to market is achieved.The co-design methodology can guide the reliability design for multi-chip integrated products.