Research On High Voltage ESD Protection Devices In Integrated Circuits

Electrostatic discharge (ESD) has been one of the most important factors impacting onthe reliability of modern integrated circuits (ICs). Since more and more electronic productsare becoming small, portable and highly integrated, the on-chip ESD protection can satisfytheir developing trends of the light weight, thin plate, low power and smart operation better.However, the high voltage on-chip ESD protection design has demanding requirements forhigh holding voltage (Vh) or holding current (Ih) and strong ESD robustness. The conventionallow voltage on-chip ESD protection solutions are thus difficult to transplant directly to highvoltage ESD protection applications. Therefore, based on the study of electrical characteristicsof fundamental ESD protection units, this thesis explores the design principles and methodsfor high voltage on chip ESD protection solutions in details. By following the technical routeof theoretical analysis, emulate and evaluate, tapeout and test, design improvement, andrepeat tapeout verification, the devices, circuits and layouts for high voltage ESD protectionsolutions are intensively investigated. Aiming at different high voltage processes and highvoltage ICs with various operation voltages, relative high voltage ESD protection deviceshave been designed and optimized. The design methods and skills are investigated andverified by combining the experimental tests and TCAD simulations. Some valuable highvoltage ESD protection solutions have been obtained and practically applied. The mainresearch content of this thesis is summarized as follows.1. For the characteristics investigations of fundamental ESD protection units, anestimation model of Vhfor bipolar junction transistor (BJT) is derived. The effect of thevertical location of reversed PN junction on the trigger voltage (Vt1) of silicon controlledrectifier (SCR) is studied. The mechanism of Vt1walk-in effect in the lateral diffusion metaloxide semiconductor (LDMOS) under multiple ESD stresses is also analyzed in details.Firstly, the diode-trigger and self-trigger NPN BJTs are fabricated in a0.6μm BiCMOSprocess. According to the experimental test and SENTAURUS simulation results, effects ofkey parameters such as Wb, Icand amplification factor on Vhare analyzed for NPN BJTsgoverned by the electrical conduction modulation effect, and the Vhestimation model isestablished by derivation, which can provide theoretical support for designing high voltageESD protection devices. Then, a series of lateral SCR, modified vertical SCR and modifiedlateral SCR with different vertical locations of reversed PN junction are fabricated in a0.25μm Bipolar-CMOS-DMOS (BCD) process. The transmission line pulse (TLP) test andSENTAURUS simulation results confirm that the Vt1of these ESD protection devices is notonly related to the doping concentration of reversed PN junction, but also depends on thevertical depth of reversed PN junction. Finally, a series of LDMOS and SCR-embeddedLDMOS (LDMOS-SCR) are fabricated in a0.5μm BCD process and stressed by multiplealternated TLP/DC pulses. TLP test and SENTAURUS simulation results show that the Vt1walk-in effect can be weakened by reducing the electrical potential between the drain andsource after the LDMOS devices are triggered. Characteristics research results of these fundamental ESD protection units can provide solid theoretical basis and useful practicalguidance for high voltage on-chip ESD protection designs.2. For the research and design of high voltage ESD protection devices with high Vh, thephysical mechanisms of dual-directional SCR with gate floating PMOS (GFDSCR) andcomplementary cascaded dual-directional SCR (CCDSCR) with high Vhare investigated. Thedual-directional high voltage on-chip ESD protection devices, such as the vertical NPNtrigger LDMOS-SCR, substrate trigger LDMOS-SCR, and LDMOS-SCR with multipleconduction paths, are designed. The high voltage ESD protection devices with high Vh, suchas the modified Zener trigger SCR (MZTSCR), Zener trigger LDMOS-SCR, P-type ringresistance trigger LDMOS-SCR and high resistance LDMOS-SCR, are also designed.Firstly, the dual-directional SCR (DDSCR), improved DDSCR (IBDSCR) and GFDSCRare fabricated in a0.25μm BCD process. The Vt1of DDSCR, IBDSCR and GFDSCRdecreases from58.1V,25.1V to18.3V. Furthermore, the voltage snapback margin ofoptimized GFDSCR can be decreased to a minimum of5.6V. While for the CCDSCRfabricated in a0.5μm BCD process, the TLP test results show that it has the highest Vh,significantly reduced Vt1, and a minimized snapback voltage margin of2.8V. Secondly, thevertical NPN trigger LDMOS-SCR devices with different channel lengths are fabricated in a0.25μm BCD process for investigating the effect of channel length on the ESD protectionperformance. Testing results indicate that the Vt1and voltage snapback margin are bothreduced remarkably, although the Vhis not obviously improved. These high voltage ESDprotection solutions with small snapback and high Vhare suitable for dual-directional highvoltage ESD protection applied between input/output (I/O) and power ports. Thirdly, theP-type ring resistance trigger LDMOS-SCR and high resistance LDMOS-SCR devices arefabricated in a0.25μm BCD process. The TLP test results show that the Vhof the ringresistance trigger LDMOS-SCR increases linearly with increasing stacked numbers, while theVt1does not change obviously. For the high resistance LDMOS-SCR, its second failurecurrent (It2) is relative small, but its Vhcan be increased to27.2V or above with greatlyreduced device area. Finally, a series of lateral (LSCR), Zener trigger SCR (ZTSCR), ZTSCRwith two fingers and MZTSCR devices with the same area are fabricated in a0.25μm BCDprocess. The TLP test results show that LSCR has the largest Vt1and the smallest Vh., andZTSCR and MZTSCR have close Vt1. However, the Vhof MZTSCR with strong ESDrobustness can be increased to a maximum of14.1V, due to the Zener breakdown mechanismand asymmetrical finger-like layout design. The MZTSCR are successfully applied to thepower management IC of a certain TV set top-box transceiver module. The ESD testingresults indicate that the MZTSCR is strong to resist the latch-up risk and can pass the9kVhuman body model (HBM) ESD protection standard.3. For the research and design of high voltage ESD protection devices and layouts withhigh Ih, the vertical drain-extended MOS (VDMOS) with closed ring layout andRC-embedded LDMOS-SCR (LDMOS-SCR-HHC) are designed. Some layout designs andoptimizations for ESD protection devices are proposed, including the drain side layoutoptimization in LDMOS-SCR and the closed ring layout design of LDMOS-SCR. Firstly, VDMOS devices with stripe and ring layouts are fabricated in a0.5μm BCDprocess and tested by TLP system. Compared to the VDMOS with stripe layout, the IhofVDMOS with ring layout is increased to0.78A while keeping the Vt1lower than40V. Withthe increasing device width, the Ihcan be further increased to0.95A without changing the Vt1.Then, LDMOS, LDMOS-SCR and LDMOS-SCR-HHC devices are fabricated in a0.25μmBCD process. The resistance-capacitance coupling effect constructed through the embeddedresistance Rpand the parasitic gate oxide capacitance Cpin LDMOS-SCR helps to improvethe Ihdue to the two-step trigger mechanism. Both the TLP and DC test results confirm thatLDMOS-SCR-HHC has the smallest Vt1(about36.7V), the highest Ih(about1.1A), and thelargest ESD latch-up resistance. Finally, the layout of LDMOS-SCR is modified by replacingthe stripe N+region with a series of P+-N+implant regions at the drain side. LDMOS,LDMOS-SCR and the modified LDMOS-SCR are fabricated in a0.18μm BCD process. TLPtest results indicate that the layout modification results in the smallest Vt1and the strongerESD robustness. Furthermore, when the stripe layout is replaced by an optimized closed loopone, the current conduction uniformity in LDMOS-SCR can be improved significantly.Experimental results show that the Vt1of LDMOS-SCR with the optimized closed loop layoutcan be decreased by about50%, and the It2can be increased by about two times, comparing tothe device with the stripe layout. These ESD protection devices with high Ihprovide suitablehigh voltage ESD protection solutions for I/O ports.