Research On New ESD Devices And Full Chip Protection In High Voltage Process

High voltage(HV)device has been applied to switched-mode power supply,power management,automotive electronics,driver circuits for display panels and so forth,resulting in more portable consumer electronics products.Meanwhile,electrostatic discharge(ESD)has become an important reliability concern in HV ICs?Among these HV ESD protection devices,the SCR device is hot and attractive for ESD protection because it exhibits extremely high failure current and low dynamic on-resistance with occupying the smallest layout area.Unfortunately,the impact of extremely low holding voltage resulted from double-carrier injection and inherent regenerative feedback mechanism causes SCR to be susceptible to quasi-static latch-up or transient-induced latch-up(TLU)danger under ESD stress condition,especially while SCR is used in the power-rail clamp circuit.There are two main methods to developed the ESD protection devices with high latch-up immunity,one way is to increase the trigger or holding current of ESD protection devices above certain minimum latch-up triggered current to prevent latch-up during normal circuit operating condition,and the other way is to increase the holding voltage of ESD protection devices to be larger than the power supply voltage.The main content of the paper is summarized as follows.Compared with normal ESD devices in CMOS and HV process,this paper analyze the cause of the HV ESD devices robustness is very weak and HV ESD protection existing difficulties and challenges.Device level and circuit level of ESD protection are researched in both of 0.18-?m BCD and 12 V BJT process.Firstly,three ESD physical test models and two special test assessment models are introduced.The characteristics of four conventional ESD protection devices are researched.Four kinds of devices are introdced to solve the deep snapback of SCR bringing the latch up in details.Then,based on the research of design window of ESD protection devices in HV process and the influence of kirk effect of HV ESD protection devices,NLDMOS are studied and its robustness is improved by embedding the SCR.Self-triggered stacked silicon-controlled rectifier structure with high holding voltage has been designed and developed prone to latch-up issue,and successfully verified.It consists of an MLSCR and multiple DTSCRs to achieve the stable trigger voltage and adjustable holding voltage.Fanally,this thesis mainly explores the circuit level of whole chip ESD protection in 12 V BJT process.To guarantee discharge path between arbitrary two pins,the ESD network is necessary.Some new ESD devices are puted forward by analyzing the characteristics of 12 V BJT HV process.The design schemes are investigated and verified by combining layout and experimental tests.