Low Voltage Nanotechnology ESD Protection Device And Full Chip Network Design

Electrostatic discharge(ESD)is an event in which a limited charge is transferred between two objects with different potentials.The instantaneous high voltage and current generated by ESD will cause the semiconductor integrated circuit to fail.In recent years,mainstream semiconductor processes have progressed from micrometers to nanometers,which means that chips have smaller sizes and larger scales,and the requirements for ESD protection design have become more strictly.Full-chip ESD protection design is the focus of integrated circuit chip engineering applications.This article will combine the characteristics of nanotechnology to design ESD protection solutions for on-chip circuits,and complete the tape-out verification on the 28 nm process.The main work of this article focuses on the following three aspects:(1)Briefly introduce the current development trend of low-voltage nanotechnology ESD protection,and systematically explain the basic theory related to ESD protection commonly used in engineering applications,including four ESD test models and calculation methods of ESD design windows.The working principles of four commonly used ESD protection devices,Diode,BJT,MOSFET and SCR are are introduced in detail,and methods for optimizing the trigger voltage and holding voltage of this devices are also explained.(2)Three full-chip ESD protection schemes have been developed which work in 1.8V power supply voltage and are verified in 28 nm process,and the design window is 2.7V-6.12 V.Three types of ESD protection devices: PN junction diodes,MOSFETs,and LVTSCRs introduced in the article are used as Input/Output(I/O)port protection devices.The RC power clamp triggered by detecting the rising edge of ESD pulse is used as the protection circuit for power rail.ESD tests were performed on the packaging circuits of the three full-chip protection schemes.The results show that all three schemes meet the test requirements of 2KV HBM and 400 V CDM.And this article also analyzes a failure I/O in a 3.3V power supply circuit.The four methods of OBRICH hotspot location,circuit simulation,TLP test,and process analysis are used to verify the failure mechanism.Finally,two improve solutions are proposed.(3)In terms of the problem that the chip area consumed by the traditional full-chip ESD protection network is too large,a compact compound SCR(CCSCR)is innovatively proposed.CCSCR internally parasitics three SCR discharge paths and three diode discharge paths.It uses intrinsic parasitic SCR and ESD diodes as the main ESD discharge path and it can independently implement six ESD discharge modes(PS,PD,NS,ND,DS,SD).Full-chip ESD protection can greatly reduce chip area consumption and achieve high ESD robustness.TCAD(Technology Computer-Aided Design)simulation results show that the proposed CCSCR has a lower trigger voltage and a higher holding voltage.In addition,the RC detection circuit is used as the external trigger circuit of the CCSCR,which can further reduce the trigger voltage of the main discharge device SCR.