Research On New ESD Protection Devices Of Integrated Circuit

As the semiconductor process has scaled down,Electrostatic Discharge(ESD)results in more and more electronics failure,and has attracted more and more attention.As a result,ESD protection design of integrated circuits has become an indispensable research in chip design.In particular,with the reduction of the process dimension,thinner gate oxides and shallower junctions lead to lower breakdown voltages.As a result,the ESD design window has become much narrower.At this time,the research of ESD protection devices with low trigger voltage,low on resistance and high robustness is becoming more significant for full chip ESD protection.As the most area-efficient ESD protection devices,SCR(Silicon Controlled Rectifier)possesses low on resistance and great ESD robustness except the high trigger voltage.Thus,reducing the trigger voltage by trigger-assistant will make it become the best choice in low voltage ESD protection.This dissertation focuses on SCR with low trigger voltage which is suitable for low working voltage,aimed at the of layout optimization,bidirectional ESD protection,high-temperature stability and the reliability of triggerassistant.The main contents of this dissertation are summarized and given below:(1)Compared the structure and layout of DCSCR(Direct-Connected SCR)and traditional SCR,DCSCR has disadvantages such as large layout area,reduced effective metal width,and lack of reverse ESD protection path.For the former two problems,a new structure of ERTSCR(Embedded Resistor-Triggered SCR)is proposed,which exhibits lower trigger voltage due to series diode chains and embedded deep N-well resistor.The porposed ERTSCR will consume 10% less silicon area,while has a larger metal width.Aiming at the latter problem,a new DDCSCR(Dual-Direction DiodeConnected SCR)with two symmetrical ESD path is proposed,which still has lower trigger voltage determined by two diodes.Without any external reverse path,DDCSCR is more area-efficient ESD protection device for input/output port in full chip ESD protection.(2)By study of the trigger mechanism and process of DTSCR(Diode-Triggered SCR),a new trigger mechanism with parasitic resistors generated by back-end process is proposed.And based on that,a new TSDTSCR(Thermal-Stable DTSCR)is proposed.Using the parasitic resistances of contacts,vias and metal wires which have positive temperature coefficient to compensate the decline in trigger voltage caused by diodes in high temperature,the experimental results show that trigger voltage drop of TSDTSCR can be reduced to 13.49% comparing to 27.18% of DTSCR.Coupled with the increasing parasitic resistances on external diode-chain,the trigger voltage drop of improved TSDTSCR can be reduced to 5.61%.At a meantime,the new TSDTSCR has a rising holding voltage at high temperature.(3)DTSCR is triggered by current injected from diode-chain which has a large area,and it cannot be triggered occasionally.Base on this,a new NCTSCR(NMOS-Chain Triggered SCR)is propose to optimize the layout and the reliability on triggering.The NCTSCR has an embedded NMOS structure in main SCR whose gate is controlled by an external NMOS-chain.When the NMOS-chain turns on,the embedded NMOS truns on and thus the main SCR is triggered.The NMOS-chain in NCTSCR will consume 31.10% less layout area comparing with diode-chain in DTSCR.At the same time,the precise threshold voltage control of NMOS also improve the success rate of SCR triggerring.(4)A new PB-GGNMOS(P-Base Gate-Grounded NMOS)is propsed to improve the ESD robustness.The PB-GGNMOS utilizes the inherent P-Base layer in BCD process,and alleviates the current concentration effect caused by light doping drain process effectively.Without increasing the device area,process layer and production cost,PBGGNMOS improves the ESD robustness of traditional GGNMOS by 15.38%.