I/O Circuit And Its Full-chip ESD Protection Design Based On 28nm High-voltage Technology

As a bridge between the internal circuit of the chip and the outside world,the input/output(I/O)circuit unit is very important in the chip.It not only needs to be able to have sufficient output capacity to the outside world,accept external signals and transmit them to the inside of the chip,but also it is necessary to provide indispensable electrostatic discharge(ESD,Electro-Static Discharge)protection for internal circuit and itself.With the continuous development of integrated circuit technology,the integration of chips is higher,the number of transistors and chip pins is increased,and the gate oxide layer is thinner.In order to adapt to different functional requirements,the design of I/O circuits is becoming more and more complicated and difficult,and the ensuing ESD problems based on I/O circuits are more severe.For many devices that require high-voltage drive,the design of high-voltage I/O circuits is essential,and the ESD protection design under high voltage is also particularly important.Based on the normal voltage I/O circuit theory,this thesis constructs a complete design frame of high voltage I/O circuit.The level shifter circuit is improved,and a double-isolated level shifter circuit is proposed to achieve level shifter at a lower input level;the improvement of the digital logic control circuit is used to reduce the output stage transient series current,etc.Afterwards,the feasibility of each module and the overall design scheme of the I/O circuit is verified through simulation.In terms of ESD protection,first of all,a variety of ESD protection units under high voltage are designed and tested,and the ESD protection unit with the best effect is determined through analysis and comparison.Then,on the basis of the high-voltage I/O circuit,two local ESD network layouts based on power rails and pads(PAD)are designed and suitable ESD protection units are used.Finally,according to the particularity of multiple power supply domains of high-voltage I/O circuits,a full-chip ESD protection network including power rails,PADs,internal circuits and I/O circuit connections,and I/O circuit internal connections is constructed.In the layout design process,the partition design of multiple power domains and the merging of cells are proposed,which greatly increases the area utilization of the layout.The above work is based on the 28 nm high-voltage process platform.Finally,the function of the I/O circuit is further verified by the simulation after the layout.The results show that the high-voltage I/O circuit designed in this thesis can transmit the low-voltage(0～0.9V)signal of the internal circuit at high voltage(-16～16V)to the outside world.The I/O circuit and ESD network designed in this thesis can provide high-voltage drive signals and provide ESD protection for external devices,which has certain reference significance for the design of some high-voltage drive I/O and related ESD protection designs.