Research And Design Of ESD Protection Of High Voltage Integrated Circuit Based On SCR

Electro Static Discharge(ESD)has become one of the main reasons for the failure of integrated circuit(IC)chips,although the research on ESD protection of low voltage integrated circuits is getting mature at home and abroad,but the research on HV integrated circuits is still in its infancy,and HV integrated circuits are usually in extremely harsh environments such as large voltage and high current,the requirements for the holding voltage of ESD protection devices are often harsh.In addition,the conventional ESD protection devices are prone to misfire,latch up and lack of robustness in high voltage integrated circuits,which aggravates the difficulties in the design of high voltage integrated circuit ESD protection.In view of this,the main aim of this paper is to improve the holding voltage of ESD protection devices,and to design ESD protective devices with high holding voltage and latchup-free immunity to meet the ESD protection requirements of high voltage integrated circuits.The main work and research results of this paper are as follows:1.This paper studies the basic theoretical knowledge of ESD protection,including ESD test models,ESD test methods,design window of ESD protection device and the characteristics of ESD protective device in an ideal state.In this paper,the working principle and performance of diode,BJT,MOSFET and SCR are deeply studied,analyzed and optimized with Sentaurus TCAD simulation tools,and the advantages,disadvantages and application scope of each ESD protection device are compared.2.In order to meet the design requirements of high voltage integrated circuits for high holding voltage of ESD protection devices,in this paper,the traditional SCR device structure is optimized to solve the problem of low holding voltage,and an innovative SCR device structure with high holding voltage(HHVSCR)is proposed,this structure is to increase the SCR holding voltage by suppressing the inherent positive feedback injection mechanism of the SCR structure.The simulation results of Sentaurus TCAD show that the holding voltage of HHVSCR can be increased from 1.88 V to 12 V under the same area of the device,and there is no effect on the trigger voltage,and the maintenance voltage of HHVSCR increases with the depth of the NIL layer.3.In order to improve the holding voltage of ESD protection devices,a stacked HHVSCR structure is proposed at the end of this paper.The premise of stacking method is that the stacking unit has a shallow snapback characteristic,therefore,this paper further optimizes the performance of the HHVSCR structure,the holding voltage of HHVSCR is further increased by adding a heavily doped P-type implant layer(PIL)under the cathode N+ region.The simulation results of TCAD show that the snapback area of the optimized HHVSCR is less than 3V,and the improved HHVSCR device structure can be stacked to improve the holding voltage.TCAD simulation results show that the trigger voltage and holding voltage of stacked HHVSCR increase with the number of stacked devices.In practical applications,the number of stacked HHVSCR devices can be adjusted to meet the ESD protection design requirements of different high voltage integrated circuits based on this scheme.