Research On Full Chip ESD Protection Based On 0.6?m CMOS Process

Electrostatic Discharge(ESD)is a phenomenon that can be seen everywhere for human beings.It can usually be produced by contact with static-charged objects.It is a small surprise in human life.But this will cause immeasurable consequences for integrated circuits(IC),thereby reducing the service life of the chip and increasing the production cost of the chip.In order to deal with ESD damage to the chip,this article will explain the project based on the 0.6 ?m CMOS process of the X-Fab process factory(XC06).Mainly divided into the following points:1.Introduce common ESD protection unit devices,such as diode,BJT,GGNMOS,SCR.It also summarizes and analyzes how to change the trigger voltage and holding voltage of the hysteresis device.For the trigger voltage,the main methods are divided into changing the breakdown voltage of PN junction,auxiliary triggering,and stacking.Among them are a.Changing the PN junction doped layer,b.Embedding polysilicon gates to reduce the base width of the parasitic transistor and shorten the current path,c.RC coupling assisted triggering,etc.For holding voltage,it is mainly divided into changing the current gain,increasing the current path,and stacking.Among them are as a.Dividing the active area to change the current gain of the parasitic BJT.b.In the conventional SCR,a new parasitic BJT is added by adding the active area to form a new current path to reduce the positive feedback,etc.2.Analyze the IO port circuit diagram under the XC06 process project.According to the definition of the design window,extract the window of the corresponding port,such as the design window between the IO port and the power line and the ground wire.A total of 5.5V-10.8V,5.5V-11.7V,5.5V-13.5V.The design window between the power supply and the ground is 5.5V-10.8V,5.5V-13.5V respectively.And based on the knowledge base of circuit-level protection,corresponding design schemes such as the protection network based on the power rail and the protection network based on the pad are proposed for this project.3.Mainly analyze the structure and TLP test results of the devices taped out under the XC06 project,so as to select devices that can meet the 8KV protection requirements and window.Among them are unidirectional protective device diodes,bidirectional protective devices GGNMOS and GDPMOS and LVTSCR.At the same time,resistor R is added to its foundation to realize RC-coupled devices GCNMOS,GCPMOS and LVTSCR?RES.The device and circuit simulation of RC coupling are done and analyzed.Then analyze the power clamp unit,such as RCMOS,RCSCR.It mainly includes the influence of RC charging and discharging on the test results,and the uneven conduction of the device caused by the layout drawing.Finally,the devices that meet the window requirements are extracted and combined accordingly to meet the full-chip protection under the protection network.