10 Bits 10MHz Self- Calibration SAR ADC

The successive approximation analog-to-digital converter (SAR ADC) is widely applied in electronics system due to its low power and relative small area consumption. With the scaling trend of transistor size in integrated circuit, SAR ADC is used to replace some pipe-lined ADC which is famous as middle-speed and middle resolution in some system, but the non-ideal factors such as mismatch, parasitic parameter, calibration technology is popularly adopted in the design of high performance SAR ADC.In this paper, it proposes a 10-bit 10MHz self-calibration SAR A/D converter, the main contents of paper is as follows:1) A bootstrapped switch which employed capacitor plate sampling principles and monotone switches to reduce the chip area and power consumption and improve the conversion rate; 2) Segment capacitor structure combined with two parasitic compensation capacitors applied in this design, in which the bridge capacitance of the segment capacitor array is integral times of the unit capacitor can enhance matching; Here we employ the calibration of parasitic capacitance to benefits the accuracy of SAR ADC, the structure can decline nonlinear errors and reduce the consumption and area; 3) Adopted dynamic differential comparator to reduce the feedback noises and improve the circuit performance; 4) The overall layout of analog and digital parts in 10-bit 10MHz Self-calibration SAR ADC is full of custom designed that the circuit optimize better oThe proposed 10-bit SAR ADC is designed and simulated using SMIC 0.18 CMOS technology. Post-layout simulation results show that at 1.8-V supply and 0.9526MHz, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB, ENOB of 9.8, the power consumption of 2.16 mW.The SAR ADC core occupies an active area of 0.35*0.52mm2.The results indicated that the structure with calibration circuit reduced the power consumption and the chip area significantly.