Analog-Front-End Key Integrated Technology For CCD High-Accuracy Singnal Processing

Charge Couple Device (CCD) has been widely applied in the fields of Modern Photonics and digital process of photoelectric image. It features many merits such as high resolution, High reliability, low noise, large dynamic range, high quantum efficiency and high charge transfer efficiency. Besides visible light, the application range is expanded to UV and X ray. The CCD signal processing system incorporates CCD array, Floating Diffusion Amplifier, Sense Amplifier, AFE (analog-frond-end) and digital signal processor. Obviously, as the front-end of the signal flow, the output of AFE has been converted to digital signal, which is not easy to introduce noise, thus, the SNR of the CCD processor is mainly determined by the performance of AFE. With the development of design and fabrication process, pixel size of CCD has been gradually reduced. Simultaneously, the frequency of charge transfer tends to be increasing, which makes the output range of CCD signal smaller. The design of AFE has become one of the central issues, especially in the high definition high speed image precessing and microelectronics.A14bit40MHz Analog Front End systerm with a programmable clock driver for CCD signal processor is proposed in this thesis. While CDS (Correlated Double Sampling), VGA (VGA-Variable Gain Amplifiers), and a14bit40MHz ADC (ADC-Analog to Digital Converter) has been integrated into the AFE. The power consumption and chip area are reduced significantly owing to the implement of a integrated CDS and VGA circuit. By adjusting the timing of SHD and SHP, the timing core offers a clock signal with a precision of530ps for CDS. One cycle of the main clock is divided into48parts equally, while a timing with tunable duty cycle is generated by programmable phase combiner to generate a optimum timing for a variety of CCD signal processors. A14bit40MHz pipelined ADC with minimizied power dissipation was designed by optimizing the per stage resolution and sampling capacitors. In SMIC0.35μm CMOS process, with a40MHz main clock and a10MHz input signal, the simulation results show that9bit VGA offer a linear gain range of0～18dB, the Gain step accuracy is0.35dB, the SNDR of CDS and ADC is no less than85.69dB and85.5dB, respectively, and the output clock with a2%～98%duty cycle, generates a less than5ps delay time error。 The chip was fabricated in SMIC0.35μm CMOS process, the experimental results demonstrate that the systerm can generate the horizontal driving clock H1-H4and reset clock RG exactly, and peak-to-peak jitter of the systerm clock is less than65.554ps which can satisfy the demand of the pipelined14bit40MHz ADC. Furthermore, the SNDRs of the two digitized pictures using the fabricated device to process the CCD signal at40MHz rate are more than45dB.