Research On 1GSps 14bit Pipelined ADC

The analog-to-digital converter is a bridge connecting the analog world and digital devices,and is an important chip that restricts modern communication systems.With the development of the times,the level of science and technology has improved,and people have put forward higher requirements for the speed of information and the quality of information.Therefore,high-performance analog-to-digital converters have become scarce products in this era.Despite this,China's related research in the field of high-speed and high-precision ADC started later than other countries,so that the current level of research and development of domestic ADC chips is far lower than the international advanced level.In addition,the import of high-performance ADC chips is subject to "Wassenaar "Agreement",which has exacerbated the urgency of realizing the national production of high-performance core chips.Among ADCs of many architectures,pipelined ADCs achieve a good compromise between sampling rate and resolution,and become one of the best ADC architectures for high-speed and high-precision signal transmission.Therefore,this thesis will focus on the key technologies to achieve highspeed and high-precision pipelined ADC.This thesis designs a 1GS / s 14-bit pipelined ADC based on 40 nm CMOS process.The ADC uses a SHA-less structure,including an input buffer and 7-stage pipeline.Among them,the structure of 2.5-bit MDAC is adopted in the first six pipelines,and the last stage is a 2-bit flash ADC.The input buffer is a necessary structure for the high-speed ADC.The input buffer and the sample-and-hold circuit connected to it are called the sampling front end.Usually,the sampling front end is the most important structure that limits the performance of the high-speed high-precision pipelined ADC.In order to improve the linearity of the sampling front-end circuit,this paper proposes to improve the traditional input buffer circuit,and on the basis of theoretical analysis,the optimization direction of the circuit is proposed.The gate voltage bootstrap switch is also a very important part of the sampling front-end circuit.This thesis also analyzes and summarizes the causes of the nonlinearity of the gate voltage bootstrap switch.In order to further improve the overall linearity of the ADC,this thesis improves the PN code injection method in Sub-ADC and MDAC,and at the same time adds a circuit that causes the comparator threshold potential to be dithered in the direction opposite to the size of Dither.By analyzing the residual curve,we can see that the output amplitude of the operational amplifier in MDAC can be reduced by half,so the linearity of the ADC can be improved.The overall layout effective area of the 1GS / s 14-bit pipelined ADC designed in this paper is 958?m?442?m,and the overall power consumption is about 1W.The postsimulation results show that at a sampling rate of 1GS / s,a signal amplitude of 1.6V,and a signal frequency within 2GHz,the SFDR of the ADC is not less than 75 dBc and the ENOB is not less than 11 bit.