| Analog front end is the key part in the analog signal quantization,which has wide application in industry control,high-defintion video,imaging sensor,wire/wireless transmission and consumer digital product.In the high-speed communication application,wireless communication has limation due to the weak anti-interference and transmission performance.In the real life,the powerline transmission network has wide distribution,low cost and convenient connection.Thus the power line communication which uses powerline as transmission channel has attracted more and more attenation,which becomes one of the most competitive technology for Gb/s data communication in room.Therefore the research of PLC analog front end with data rate extending from hundred Mb/s to thousand Mb/s and compatibility of standards ranging from low frequency band to high frequency band is very valuable and meaningful.The relevant works of PLC AFE are missing due to the following challenges:how to overcome the wide,various range of input signal power caused by the various distance between the PLC receiver and transmitter.Thus the AFE-transceiver must be designed with reconfigurable structure so as to satisfy the wide dynamic range of input signal in the real application;how to avoid the degradation in transmiting efficiency due to the impedance mismatch between transmitter and powerline,which is caused by the process deviation,air oxidation,ea al.It is necessary to design a line driver with programmable output impedance;how to design a ADC with high-speed,medium-precision performance for quantify the output signal of receiver,the ADC is needed to be designed for improving power efficiency and chip area.The SAR ADC has difficulties in achieving the high speed and medium-precision due to the chip area and precision problem.Here redundancy calibrating and capacitance restructuring technolgy are used.This paper presents a reconfigurable analog front end using 0.18?m 3.3V CMOS process.The analog front end consists of transceiver and data converter,including the analog to digital converter and digital to analog conerter.The analog front end is a key and difficult block in the PLC system.In this paper,the popular PLC standard HomePlugAV2 is decribed in detail.The system is designed based on the system analysis and specification distribution.The designed recevier includs the attenuation-programmable gain amplifier,low noise amplifier,low pass filter and programmable gain amplifier;the transmitter has line driver with programmable output impedance.In other part,a high-speed,medium-precision ADC based TSMC 65nm 1.2V CMOS process is designed with the successive approximate theory.For improving the performance of precision,speed and chip area,the redundancy calibration and capacitance restructuring technology is proposed and ahcieved.The PLC AFE transceiver has a power consumption of 160 mW(receiver)and 350 mW(transmitter)that occupies a 5.75 mm~2 die area(dual channel).The receiver exhibits a bandwidth of 100 MHz and a gain range from-26.2 dB to 21 dB,with a minimum NF of20.2 dB@maximum gain 21 dB and maximum IIP3 of 36.1 dBm@minimum gain-26.2dB.The transmitter achieves 42 d B low-band multi-tone power ratios(MTPR)and 9.6 dB high-band MTPR.In addition,the post simulation results of proposed SAR ADC show the DNL is between-0.38 LSBand 0.23 LSB,the INL is between-0.43 LSBand 0.42 LSB under the sampling rate of 125 MHz.When the input is 10.09 MHz sine wave,the FFT result shows the SNDR is 72.3 dB,SFDR is 84.1 dB,the resulted effective number is 11.72bits.It occupies an area of 0.156 mm~2,the total power consumption is 5 mW,the FOM is12 fJ/conv.This paper presents an AFE-transceiver and SAR ADC for PLC application.The circuit and layout design,simulation and measurement results are described in detail.The designed AFE satisfies the application requirement.In comparison with the existing PLC chip,the outstanding performance is ahcieved. |
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