Cmos Wide-band Scores Points Frequency Synthesizers In The Research And Design

The ultra-wideband and software defined radio (SDR) technology is now deeply involved in wireless communications. The prospective implementations of these technologies require a radio frequency (RF) front-end with wide frequency range, agile response, low power consumption and programmable feature, making the design of the frequency synthesizer a real challenge. Focusing on the LC voltage-controlled oscillator (VCO), loop bandwidth regulation and automatic frequency calibration (AFC), the∑A fractional-N PLL-based frequency synthesizer is researched in this dissertation, and the detailed achievements are as follows:After overviewed current progress of ZA fractional-N frequency synthesizer design, the basic theory of the phase-locked loop (PLL) is analyzed, and the∑A fractional-N modulation and its impacts on loop’s transient response and phase noise are discussed, followed by the introduction and compensation of deterioration caused by the loop bandwidth variation.In order to realize constant loop bandwidth and agile AFC, the thermometer-coded switched capacitor and varactor array are adopted to design a wideband VCO with constant VCO gain (Kvco) and constant sub-band interval (fstep)-This VCO is implemented under SMIC65nm CMOS technology, and the measurement results show that it covers the frequency range of622MHz-1518MHz. with Kvco and sub-band interval (fstep) of150MHz/V and99MHz, respectively, phase noise of-119.9dBc/Hz@1MHz when oscillating at1.39GHz. Furthermore, aiming at the high-frequency applications, the cross-coupled MOS, which is used as the negative resistance in VCO, is optimized and the compact model based Dn PSP is established for it. An extraction procedure for extrinsic capacitance based on PSP and an efficient method for interconnection parasitics based on vector fitting are developed. The verification results show that the proposed model exhibits improvements in accuracy and efficiency of61.8%and60.5%, respectively, compared to the PDK model. A132GHz push-push VCO is then designed using this layout optimization technology.To alleviate the variation of loop performances during the frequency shifting, the programmable charge pump (CP) is employed to regulate the loop performance across the entire frequency range.In order to accelerate the frequency shifting, the division-ratio-based direct mapping calibration scheme is proposed to work with the VCO of constant Kvco and fstep. A redundant calibration is introduced using a quarter of VCO output frequency which improves the AFC efficiency. This AFC reduces the calibration time significantly.As far as the previous analysis and design are considered. a wideband fractional-N frequency synthesizer is implemented under SMIC65nm1P8M technology. with die size of1.3mm×0.93mm. Measurements show that this frequency synthesizer covers the frequency range of40MHz-1500MHz, with fractional-N and integer-N out-of-band phase noise of-100dBc/Hz@1MHz and-120dBc/Hz@1MHz, respectively. The loop bandwidth across the entire frequency range is approximately30kHz with variation less than13.7%. and AFC consumes100ns for direct mapping calibration. The chip consumes11.7mW from1.2V supply.The design targets are achieved.