High-Performance Low-Noise Phase-Locked Loop Analysis And Design

Phase-locked loops (PLLs) are widely used in high speed digital systems to generate low jitter on-chip clocks. As system speed increases, more stringent phase noise requirements are imposed on PLLs. Previously, the design of low-jitter PLL has focused on reducing jitter caused by the individual PLL component. As a result, building blocks such as low-noise voltage-controlled oscillators (VCOs), deadzone-free phase frequency detectors (PFDs), zero-offset charge pump circuits, and low-noise frequency dividers have been widely studied. However, it is not well emphasized that the overall noise performance of the PLL not only depends on the design of the individual components, but also heavily depends on the choice of the loop bandwidth. Therefore, a more thorough analysis of the output jitter, taking into account optimal loop bandwidth selection, is provided in this paper.Based on the phase noise properties extracted from the individual components, by means of the low-pass or high-pass transfer characteristics of different noise source to the output, an optimal loop bandwidth design method, derived from a continue-time PLL model, further improves the jitter characteristics of a PLL, in this paper. The described method firstly finds optimal loop-bandwidth on basis of actual power density spectrum of the individual components, and then achieves optimal loop-bandwidth by changing the value of resistor or charge pump current. A 400MHz low-noise PLL on the basis of previous design strategy is designed in 0.18 um CMOS process, finally. The main content includes the following parts.1. The traditional design method and modeling theory of the charge pump PLL (CPPLL) with high-performance are studied in this paper. Specifically, the traditional design method of the charge pump PLL is summarized, based on a simplified second-order model, and PLL circuits is modeled more accurately in ADS to guide system design;2. The noise mechanism and spectrum properties extracted from the individual PLL components are researched here, and actual power spectral density of phase noise from each components is measured by HSPICERF to verify the correctness of the previous theoretical analysis;3. The low-pass or high-pass transfer characteristics of different noise source to the output is investigated, and it is showed that the overall output phase noise depends on -3dB bandwidth of different transfer functions from each noise source to the output, then a phase-domain model in ADS is presented to predict different noise performance of a PLL at different loop bandwidth accurately;4. An optimal loop bandwidth design method of low-noise PLL is proposed, in which a new computational method of circuit parameters based on a third-order model of PLL is also introduced;5. On the basis of an optimal loop bandwidth design method of low-noise PLL, a new kind of programmable PLL with high-performance and low-noise is designed under the 0.18μm CMOS process. Simulations and emulations have shown that PLL output clock has very good jitter performance, the RMS and peak-to-peak jitter of the PLL are 9.634 ps and 50.289 ps, respectively.