Research On Robust Timing Technology Based On Ultra-clean PLL

With the development of social economy,the current national infrastructures such as power,communications,transportation,and finance require high-precision time benchmarks to support large-area,large systems to achieve precise time synchronization.Since the global navigation satellite system has the characteristics of global coverage,all-time,all-weather,high precision,simple receiving equipment and low cost.The satellite timing technology has become the main timing means for high-precision time synchronization.At present,the electromagnetic environment is becoming more and more complex,interference and spoofing technology is gradually emerging,navigation signals are vulnerable to interference and deception and affect timing accuracy,thus causing great losses.In order to achieve high precision and robust timing,abnormal detection of the input of phase offset information of the ultra-clean phase-locked loop of the timing receiver is required,and noise purification of timing signal is also required.This paper studies the robust timing technology of ultra-clean phase-locked loop and obtains the following research results:First of all,analyze the working principle of timing receiver,discusses the characterization of timing time of signal and noise theory,given the SSB phase noise and Allan variance index of an oven controlled crystal oscillators and a cesium clock,the clock offset simulation data is obtained by power-law spectrum model,the simulation data indicator curve is completely consistent with the given index curve,the rationality of the power-law spectrum model is verified.Then the basic principle of PLL,the order and type of loop,and the parameters of loop are introduced.In addition,the natural frequency and loop gain were selected as the bandwidth of the loop respectively for simulation analysis,and the simulation found that under the appropriate damping coefficient,the selection of loop gain as the loop bandwidth had a better characterization of the loop transfer function and error transfer function at the turning point.Then,in view of the fixed position of most timing receivers,a robust timing technology based on joint verification of position domain and clock offset domain was proposed to detect the abnormal signal of the input timing signal of the ultra-clean PLL,and the working flow chart of the joint verification was given.In the location domain test,the decision threshold of the location domain is verified by 95% positioning results of the measured data.Then,the recursive forgetting least squares algorithm is proposed to detect phase outlier and phase jump abnormalities.The updated clock offset can be used to tame crystal vibration reasonably for robust timing.The processing error of the clock difference detection algorithm is less than 0.2ns.Finally,in order to purify the time-scale signal noise,this paper proposes a two-order digital phase-locked loop(PLL)technique.This paper analyzes the relationship between loop bandwidth and time constant,the selection of loop bandwidth and time constant,and provides the basis for the design of loop parameters.The power law spectrum model is used to simulate the frequency source signal.According to the previous analysis,the selection of the time constant and the second-order DPLL proportional coefficient is simulated and analyzed.The output signal integrates the advantages of timing signal of cesium clock and oven controlled crystal oscillators OSA,achieving both short-term and long-term excellent frequency stability.The research results of this paper can be applied to the high-precision satellite timing receiver and the ultra-clean phase-locked part can also be used in other areas that need to purify the frequency source signal.The timing anomaly detection method and ultra-clean phase-locked technology proposed in this paper can ensure the timing receiver's robustness and provide high-precision time frequency reference.