Simulation Analysis And Design Implementation Of The Phase-locked Frequency Synthesizer Circuit

With the development of science and technology, as an automatic phase feedback system, the phase-locked loop has been widely used in a number of electronic field.The phase-locked loop has many advantages, which include its narrow-band tracking,no frequency deviation, low threshold, ability of anti-interference and ease of integration. In the process of phase-locked loop design, the loop bandwidth is the most important parameter to the success of the whole design. On the one hand, the loop bandwidth will affect the acquisition belt and acquisition time, which on behalf of the acquisition performance; on the other hand, the output phase noise of the loop not only relates to the phase noise model of each device, but also depends on the selection of the loop bandwidth. Therefore, this article has a deep discussion and research about not only the relationship between the acquisition performance and the loop bandwidth, but also the impact of the loop bandwidth on the output phase noise.First, the article starts with the basic theory of the phase-locked loop. With the simple second-order phase-locked loop as an example, the article analyzes theoretically the relationship between acquisition performance and the output phase noise model. Then, in ADS circuit simulation software, the phase-locked loop circuit models based on different structures of PLL loop filters are built and simulated in time-domain and frequency-domain. These simulation are done to verify the theoretical analysis. Secondly, a high-performance PLL frequency synthesizer based on PLL chip PE3236 is designed. Finally, the PLL frequency synthesizer is debugged and tested. The loop bandwidth is changed by adjusting the parameters of the circuit,and the acquisition time and loop output phase noise are tested in different loop bandwidth. The test results are in accord with the theoretical analysis.