The Research And Design Of TD-SCDMA Divider

As the arrival of3G, communication system and communication industry produced very big change, TD-SCDMA3G has been used as one of the standard. The TD-RFchip is a bottleneck of TD-mobile. We firstly analyzes the RF chip module transceiver and receiver structure, with intermediate frequency transceiver and zero intermediate frequency transceiver comparison, determine the use of zero intermediate frequency transceiver and reciver structure, and the transceiver of the main parameters are analysed.The phase lock loop frequency synthesizer principle was analyzed. There are different divid with different type feedback divider. The integrator frequency synthesizer, dual-mode frequency synthesizer and fractional frequency synthesizer was analyzed separately. There are some discuss on performance influence with PFD, VCO and divider. The whole TD-SCDMA frequency synthesizer system performance was simulated by Matlab.The parameters and basic principle of LC oscillator were analyzed, and the influence of the MOS parasitical parameters to oscillator was considered. We summarize the VCO design approach, and the complementary cross coupled LC VCO is chosen, the MOS size and the resonance network out of the chip is designed. Then, the VCO circuit simulation was implemented by Spectre which is the analog circuit simulation tool of Cadence.The principle and specification of phase frequency detectors(PFD) was analyzed. The structure of PFD, such as precharge PFD, common edge trigger PFD, TSPC dynamic structure PFD and SCL structure PFD was introduced. The characteristic and design approach of SCL inverter and latch was emphases discussed. The advantage is low noise, high gain and slew rate, which is very suitable for RFIC.Aiming the low power RF decimal frequency divider structure are analyzed in detail, the main power consumption and phase noise from high frequency part. Analysis of frequency divider type, considering the low power consumption, the function design and other factors, no longer choose the traditional digital logic structure dual modulus divider, but switched to more advanced phase conversion type dual modulus divider. Phase converter through the signal phase switching method N/N+1switching to lower working frequency, thereby reducing power consumption. At the same time the forward phase converter at work will collapse the glitch issue. if not effectively control,The circuit will not work. Through the concrete analysis of collapse burr produced is due to signal the phase mismatch caused by the switching signal, the two did not find a suitable switching point. In view of this situation, use the Rising edge of second signal to the drive phase switching module, without adding too much design and the power consumption of the case to solve the problem better. The divider phase noise and power consumption analysis, frequency divider phase noise and power consumption are mainly from the first RF fixed two dividers, determines the module design is to reduce the power consumption of the key. The injection locking principle applied in the fixed two divider on the likelihood.The fixed two divider is looked as a ring oscillator, by reasonably setting the oscillator frequency of free oscillations, achieve maximum swing through the signal, signal oscillation mode to reduce power consumption. The structure of CML circuit is suitable for RF circuit design for low power and RF frequency. The design of RF fixed two frequency divider, phase switcher, asynchronous divider chain, MASH Delta-Sigma decimal modulator, the output Buffer. Divider module working in GHz above, the divider can be achieved5.056-5.750decimal frequency divider.