Design Of Crystal Oscillator And Its Application In Frequency Synthesizer

With the continuous rapid technology development in digital TV, communication, GPS, radar, navigation, remote control and remote measurement areas, requirements for the frequency stability, the frequency spectrum purity, the frequency range and the number of output frequencies keep increasing for frequency sources. In order to improve the frequency stability, high precision frequency-controllable oscillator and frequency synthesis technology have been widely adopted to generate high quality frequency source. As a critical component in modern electronic systems, the frequency synthesizer can generate one or more frequencies from single or multiple frequency references. The frequency synthesizer has been widely applied in various areas of current information technology industry, having many potential applications and an explosively growing market. In this thesis, in-depth research has been focused on the theory, design and implementation of the digitally-controlled crystal oscillator (DCXO) and the fractional-N frequency synthesizer.The first part of this thesis presents a comprehensive analysis of oscillator-related technologies, as well as their applications in frequency synthesizers in recent years. Then, from the practial viewpoint, the thesis describes the designs of an integreated DCXO and a Sigma-delta fractional-N frequency synthesizer which are used in the digital TV tuner based on the national DMB-TH stantard, A complete set of design methods and processes are formed from the system-level design, the behavior-level design to the circuit-level design. The designed DCXO adopts Pierce architecture. The frequency drift correction is done by using a 6-bit automatic frequency control (AFC) signal generated by the feedback correction loop between the oscillator and the base band. The long term stable frequency output has been obtained. The simulation at 1.2 V power supply shows that the tuning range is 72 ppm@24 MHz, and the frequency step per AFC code is 1 ppm. The start-up time is about 900μs, the peak-to-peak oscillation amplitude is 0.8 V, and the phase noises at a deviation of 1 kHz and 10 kHz are -141 dBc and -145 dBc, respectively. All except the quartz crystal are integrated on chip. The PLL-based fractional frequency synthesizer possesses wide frequency band and fractional-N capability. Using the Sigma-delta fractional-N frequency control and information center regulation, it can meet the requirement of a digital TV receiver chip for local oscillation signals of each band. The phase frequency detector (PFD) circuit is constituted with the dynamic D flip-flop (DFF) and the delay circuit can, which can effectively overcome the dead area, and have high-speed and low power consumption features. The voltage-controlled oscillator (VCO) uses the digital tuning technique, which increases the frequency tuning range effectively.Another creative design in this work is about the reference used in the circuit. A temperature compensation method based on matching improvement has been proposed. A practical bandgap reference source with low temperature coefficient and high precision has been implemented by using a new BiCMOS low-voltage cascode circuit structure. HSpice and Cadence Spectre are used for typical circuit simulation. Results from Monte Carlo simulation and analysis of process corners indicate that the matching improvement method is feasible and correct. The circuit has a temperature coefficient of 8.85 ppm/oC in the temperature range from ?40 oC to 80 oC, and a power sensitivity of about 0.516%.The DCXO and frequency synthesizer designed in this work adopt TSMC mixed/RF 0.13μm RFCMOS process. They can be used in digital TV receiver chips and have been fabricated.