The Research And Design Of Low Jitter Plls With Wide Frequency Range

Phase-Locked Loops (PLLs) are widely used as clock generators for digital systems, frequency synthensisors for wireless communication and clock/data recovery circuits. As the clock frequency increasing, digital systems have strict requirements for clock signals'jitter performance. If a PLL could achieve low jitter output signal in a wide frequency range, it can be used in digital systems which have different frequency requirement. Therefore, it is not necessary to design special PLLs for each ASIC and the low design and verification cost is achieved. This research focuses on designing a low jitter PLL in a wide input/output frequency range.The PLL sub-blocks and system design requirements that influence the PLL general performances are enumerated, through analyzing the PLL operating principle, structure and charge pump PLL theory. The loop delay's influence on the loop stability is analyzed. Since the pole delays the feedback signal, the loop delay can also be regard as a pole. The delay value which affects the loop stability is reversely proportional to the loop bandwidth approximately. The open loop transfer function with a delay equivalent pole makes it possible to use the classic s domain analysis method, considering the delay's influence.The charge pump PLL noise and jitter properties are studied. Through previous research of oscillator phase noise models, the oscillator noise is analyzed based on the linear time variant model, considering the nonlinear property under strong noise environments. Noise sources in PLLs are studied, with emphasis on the thermal noise, the 1/f noise, the digital switching noise in application environments and their influence to the output signal noise. Given the noise power and the technology condition, the oscillator and PLL output signals'noise power spectra can be computed according to noise models and noise transfer functions. Under the condition of a dominant oscillator noise, a peak value appears in the power spectra with an offset frequency of the loop bandwidth because of the high pass property of the oscillator noise. Therefore, the loop bandwidth should be maximized to lower the peak value and reject more noise in oscillators. However, the ratio of the loop bandwidth and the reference frequency can not exceed a certain value. The low jitter design principles for this kind of PLLs are that the loop bandwidth tracks the reference frequency and the loop stability is ensured at the same time.The adaptive bandwidth PLL design method and a new PLL structure are presented. Classic charge pump PLLs can only achieve the most optimized output jitter performance in a perticular operating condition. Adaptive bandwidth PLLs can dynamicly adjust PLL parameters to achieve a low jitter output signal under any operating conditions. These charactors include a bandwidth tracking the reference frequency and a fixed damping factor. The presented adaptive bandwidth PLL design method for clock generators regards the PLL as a proportional and an integral control loops. The adaptive bandwidth PLL's reqirements to these two loops are researched. The proportional and the integral control loops should be proportional to the reference frequency and the square of the reference frequency separately. Furthermore, the previous self-biased PLL structures'drawbacks are explained using this method and improved structures are proposed. A new current mode self-biased PLL structure which has a wide frequency range is presented. A current controlled oscillator is used and the two control loops are implemented independently. The proportional loop is implemented by the current over rush derectly and the charge pump current is proportional to the oscillator control current. However, the proportional factor of the integral loop charge pump is controlled by the reference frequency. The PLL new structure resolves problems that the classic self-biased PLL's loop stability is restricted by the frequency division ratio and the current mode self-biased PLL's loop stability is restricted by the reference frequency. A wide input/output frequency range and frequency division range could be achieved and the independence of process, power and temperature (PVT) is kept.The PLL design and measurement results are presented. The wide frequency range current mode self-biased PLL's circuits and layout designs are finished and the loop stability is verified through post simulations. A wide input/output frequency and frequency division range are achieved. Furthermore, a self-biased PLL is designed and fabricated in a 90 nm digital CMOS process and low jitter design principles are verified. Measurement shows that the PLL achieves low jitter ouput.