Design And Implementation Of Low Jitter 80MHz Ring-PLL

Phase-locked loops(PLLs)are widely used in wireless radio frequency communications,optical fiber communications,high-performance digital circuits and other fields.In many application fields,stable and accurate clock signals are essential in high-performance circuits.The low-jitter PLL in this paper is used to provide sampling clock signals for high-speed ADC.To ensure the sampling accurately of the analog input signal and the high signal-to-noise ratio performance of ADC,a stable and accurate clock signal is required.Based on noise optimization technology and consideration of system stability analysis,this paper designs and implements a PLL with low phase noise and low jitter under the SMIC 40 nm CMOS process,which also uses a novel high-performance charge pump circuit,and the charge pump improves the current mismatch and achieves high output voltage swing.And the use of noise suppression technology significantly improves the jitter performance of PLL.The work and main innovations of this paper are following.(1)The paper introduces the working principle of the PLL with low jitter and low phase noise,and puts forward the key points in the design,including low phase noise,system stability and charge pump current matching,etc.And finally proposes the system structure and design parameters of the PLL.(2)The paper analyzes the noise of each sub-module in PLL.On the one hand,the noise transfer function of each sub-module is derived.On the other hand,this paper combines to the module noise and the noise transfer function,analyzing theoretically the noise contribution of each modules to the output phase noise.Therefore,a specific and feasible noise optimization program in the perspective of circuit design is put forward.(3)The circuit design of each module of PLL in transistor level is completed in this paper.Firstly,the noise optimization points of each module are introduced.Secondly,it gives the details of the circuit design in each module,including theoretical analysis and deduction,design parameters and simulation results verification.Finally,the paper summarizes the design and realization of the overall circuit.(4)In charge pump circuit,the non-ideal effects are deeply studied,and the non-ideal effects including charge and discharge current mismatch,charge sharing,clock feedthrough.A novel low current mismatch and high voltage swing CP circuit is proposed in this paper,and the charge sharing and clock feedthrough are also efficiently solved.In addition,the source switch of the circuit adopts current rotation technology,which greatly reduces the turn-on time of the CP.(5)Considering both of noise and power consumption of VCO,this paper adopts a pseudodifferential inverter unit and adjustable RC branch,and adds a positive feedback load to increase output amplitude and conversion rate.Without sacrificing low noise performance,the supply voltage is reduced to 0.9 V to save power consumption.(6)In response to the requirement of low jitter,meaning low phase noise,phase noise suppression technology is adopted,and its influence on the noise transfer function of each module is discussed.The RMS jitter of the PLL with the scheme is reduced by 1.5 ps,improvement of nearly 39%,without sacrificing system stability.The low phase noise and low jitter PLL in this paper,achieves a phase noise lower than-124 d Bc/Hz @1MHz,and the RMS jitter is less than 3.8 ps,and the power consumption is 1.1 m W.In addition,it also uses noise suppression technology to reduce the noise contribution of the charge pump and the ring oscillator.Therefore,the jitter is reduced by 1.5 ps(39%),and power consumption is 2.36 m W,which means the noise suppression technology apparently improves the jitter performance of the PLL.Among them,the use of a novel high-performance charge pump circuit achieves low current mismatch characteristics(<1%)and high output voltage swing(0.04V?1.07V)under 1.1V supply,ensuring the low noise of charge pump and greatly improves the tuning range of VCO.It is worth mentioning that the charge pump circuit can resist the influence of process fluctuations and random mismatch.