Modeling And Design Of Charge Pump Phase-Locked Loops

This dissertation presents a study on modeling and circuit design of Charge Pump Phase-Locked Loops (CP-PLL).In the aspect of modeling, we have a brief discussion on a linear model and z-domain discrete models of CP-PLL, analyzing their contributions to circuit design and pointing out their merit and demerit. Based on above analysis, we propose a novel z-domain model for CP-PLL, and give a detail derivation and an explicit explanation for the model from the view of ampled-data system. Comparison and verification results are provided with MATLAB and Spectre, which fit well with existing models. What's more, the proposed z-domain model can successfully guide and shed light on PLL circuit design.In the following charpts, by Wiener process theory, we give closed-form expressions for phase noise and jitter of free-running oscillator in general case. Combined the expressions with the proposed z-domain model, the timing jitter of CP-PLL output related to different noise sources in the loop are also investigated in z-domain: Residue theorem is adopt to simplify the calculation, and optimize the noise bandwidth in terms of the PSDs of VCO and input reference clock, which is instructive to design the loop parameters.In the aspect of circuit design, a new Current-Mode Filter (CMF) is presented to reduce the area of on-chip capacitor. The technique not only greatly shrinks the chip area, but is easy to implement, moreover, Contrast with other reported methods, the proposed CMF is of advantage in self-biasing and low voltage, and have no need to use opamp or floating capacitor, which simplify circuit design greatly.An improved low-noise ring oscillator is explored utilizing Negative-skew configuration, which has a low power-delay product. Simulations demonstrate that our VCO is comparable with other reported design on phase noise performance.An adaptive bandwidth CP-PLL is built based on the new CMF, Negative-skew VCO and other conventional components. The loop is robust and its bandwidth is independent of process, power supply, temperature and multiplication factor N. When multiplication factor N changes from 10 to 100, simulation demonstrates that the bandwidth varies 30%, while 90% to conventional CP-PLL.A high performance crystal oscillator circuit is designed to generate a reference clock for high density CP-PLL. Meanwhile, the relationship between oscillation amplitude and bias-current are anlysized and some practical circuit simulation techniques are also perfomed for high Q circuit.Finally, the above circuit prototypes are fabricated in standard CMOS process. The measurement results show: VCO's tuning range and power consumption are consistent with the simulations, and it has good jitter performance; the CP-PLL also functions well, compared with other reported design, it is also competitive in terms of power consumption and jitter performance; the reference clock (crystal oscillator) qualified for CP-PLL has better (power and jitter) performance than some products on the markets.