Design Of High-performance Current-mode Adaptive Bandwidth Phase-locked Loop

In System-on-a-Chip(SoC),phase-locked loop(PLL)is generally used to uniformly integrate various clock signals required by the system.As the core driving module of the SoC,the clock generation circuit has strict requirements on the output frequency range,output noise performance,duty cycle,phase uniformity,power consumption and area of the clock signal.In order to meet the working requirements of each module of the SoC,this paper designs a low-jitter multi-phase clock generation circuit with a wide range of output,which is implemented using a current-mode adaptive bandwidth phase-locked loop architecture.This article starts from the stability and noise transmission characteristics of the traditional second-order charge pump PLL,and complete the system modeling of the loop stability and noise of the PLL,which is used to guide the stability design of the phase-locked loop Then,the locking mechanism of the adaptive bandwidth phase-locked loop is described,and the design method and improvement strategy of the phase-locked loop in this paper are given.Compared with the traditional second-order charge pump PLL,this design uses a self-biased charge pump(CP)and a digital to analog converter(DAC)circuit to achieve the purpose of adaptive bandwidth.This article proposes a new type of Current-Controlled Oscillator(CCO)structure,which uses a three-stage single-ended CMOS inverter current-controlled oscillator structure to provide a wide range of low jitter output.The oscillator output By adding an AC buffer and a Two-Division Quarter-Phase(TDQP)circuit to meet the system's requirements for phase separation and duty cycle.In addition,since the entire loop is self-biased,a quick lock circuit is added to avoid possible non-starting risks,and a pre-frequency divider and a post-frequency divider are added to adapt to the needs of a variety of working environments.The loop bandwidth of the adaptive bandwidth PLL changes only with the change of the input reference frequency,and it has a wide input and output frequency range.In addition,by systematically modeling the loop stability and noise of the adaptive bandwidth PLL,guide the selection of the best bandwidth position to optimize the output noise performance of the PLL,achieve a wide input and output frequency range while having lower clock jitter.Since the entire loop is self-biased,there is no need for an external reference voltage/current source in the self-bias loop,which improves the resistance to drift characteristics of Process,Voltage,and Temperature(PVT)to a certain extent,and expands the achievable range of loop bandwidth.Based on the TSMC 22nm Fin FET device process,this article uses Cadence and MATLAB software tools to assist in the completion of the PLL circuit and layout design,and completes the front-end simulation verification of the system,and finally performs tape-out and test verification,The chip test results show that the PLL function is normal.Under normal temperature and 3.3V power supply,the PLL can operate in the output frequency range of0.8GHz to 3.2GHz.The measured phase noise is-107.2d Bc/Hz@1MHz and the jitter RMS value is 3.36ps in central frequency at 1.92GHz,and the core chip area is 0.04mm~2.The power dissipation of the PLL core is only 4.2m W.According to the test results,various performances can meet the requirements of better design indicators and can meet the application requirements of the actual SoC.