Design Of Broadband Reconfigurable Low Jitter Phase-locked Loop

In order to meet the protocol requirements of different transmission rates,serial data transceiver circuits such as high speed serializer and deserializer(SERDES)need to send and receive data at different rates,which makes the bandwidth demand of the transceiver lager and larger.On the other hand,the jitter of serial data is mainly determined by the on-chip high speed clock,and with the increase of the data transceiver rate,the requirements for the sampling clock are also higher and higher,which further improves the performance requirements for the sampling clock.Therefore,the clock source for SERDES applications requires both a sampling clock that outputs a wide range of frequencies and a sampling clock with low jitter.Based on the application requirements of 6Gbps serial signal transmitter,this paper mainly studies a wide-band low-jitter self-biased phase-locked loop.The main research contents include:(1)In order to realize the performance of PLL output clock with wide range and low jitter,a reconfigurable broadband and low jitter PLL based on self-biased structure is designed in this paper.By designing a frequency division modulus detection circuit,the PLL frequency division modulus and the charge pump current are matched to realize the broadband and low jitter self-biased PLL.(2)In order to ensure the integrity of the high-speed signal and avoid the output jitter caused by the transmission loss of the high-speed signal caused by the reflection of the impedance mismatch,the impedance mismatch problem is solved by using the pre-weighting and adaptive impedance matching technology and achieves the output impedance match of the transmitter,so as to reduce the output jitter of the transmitter.Phase-locked loop and the transmitter circuit design use 40 nm CMOS technology,and based on the chip testing,its results show that the self-biased phase-locked loop has 7the same reconfigurable charge pump structure,which can realize 25?A?325?A range of output current,and multimode frequency divider can achieve 4?100 frequency division,implementing 1GHz?3GHz low jitter clock output and meeting the demand of 2?6Gbps serial data sending.At the transmission rate of 2Gbps,the output RMS Jitter is 4.7ps and P-P Jitter is 37ps.At the transmission rate of 6Gbps,the output RMS Jitter is 2.7ps and P-P Jitter 36ps,which can meet the requirement of 10^-12 bit error rate at the whole transmission rate.