Studies On Low-Cost Test Methodologies For Network On Chip

As the advance in technology and the decrease in feature size of electronic components, more and more intellectual property (IP) cores can be integrated into a chip. Communication between more and more IP cores on System on Chip (SoC) makes a heavy burden of the bus. The conception of network on chip (NoC) has emerged to solve various bottlenecks during bus applications. In recent years, multiple core architecture has been widespread concern because of its large-scale parallel processing capability. More and more cores will be integrated on a chip. Multi-core chip design and testing will be a new hot spot for future research. Currently, NoC design and test models are mostly based on 2D-mesh structure. Data communication mainly contains three ways:unicast, multicast and broadcast. However, as the number of cores increasing and the multi-core widely applied, the shortcomings of 2D-mesh structure will exposure gradually. Furthermore, in NOC test research area, other topologies for multicast data communications have not been proposed completely. To solve these problems, this thesis mainly carries out the following works.Firstly, this thesis compares 2D-mesh and butterfly fat tree (BFT) topologies of the network performance by simulation, and proposes that NoC deployment should be used BFT topology for multi-core chips in future.Secondly, to reduce test application time, communication network loads, test load and storage space of the automated test equipment (ATE), this thesis implements a multicast test scheme which can compare test data in a router. This thesis also designs node coding, data package format in multicast test routing protocol and comparative features of the router in the NoC with BFT structure. The experimental results show that, the proposed method is more effective to reduce test application time and ATE memory size than the traditional 2D-mesh topology based on the unicast and multicast method. The test application time is reduced up to 96.03% and 60.41% compared with unicast and multicast methods respectively for the circuit used in the experiment. The ATE stored cost is also reduced to 52.29% of that of previous methods. In addition, the proposed method reduces the total energy consumption significantly compared to the two methods introduced above, which will provide larger trade-off space for test application time and test power consumption. Finally, by analyzing the test application time in the case of virtual channel assignment or not, we concluded that the proposed method is applicable to virtual channel technology.