The Design Of Multifunctional System Based On Broadband Access Network Chip Test

With the rapid development of communication technology, and the extensivedemand for broadband access, a variety of functional networking chips came intobeing with it. Due to the complexity of the broadband access network ing chip test,develop multi-functional and versatile test system which has a good application valueof improving the networking chip test efficiency and R&D efficiency. Amultifunctional system based on broadband access networking chip test is proposed inthis paper. It mainly includes multifunctional test board and chip test backplane, notonly can test power module, clock module, communication interface module ofnetworking chip, and can process a variety of broadband access services.Based on the system architecture design, there are some disadvantages abouttraditional system architectures including waste of resources, too many external testequipments, high damage rate of PCB and so on. A new kind of system architecture isproposed in this paper: it consists of multifunctional test board and chip test backplane.Unlike traditional architectures, multifunctional test board involves FPGA and clockfrequency and phase offset modules. These modules make multifunctional test boardprocess and test the capabilities of all kinds of Media Independent Interface, andreduce the dependence of test system to external equipment.Based on reliability of system design, in order to overcome the problem ofinstantly producing pulse current lead to devices damage on PCB, due to the voltageacross capacitor at power supply input port is not changed abruptly when powering onsystem. And in order to meet the test about test chip supply, so an improved slow startcircuit is proposed in this paper. In the basis of the original slow start circuit whichavoid producing pulse current and support PCB hot-swappable, the improved slowstart circuit introduces optical coupler. The optical coupler collector and emitter arerespectively connected to NMOS source and gate, and program FPGA to outputaccurate timing change state of optical coupler, in order to complete test of timingrelationship between the test chip supply and reset or clock. The test system is tested by testing a network chip is designed by company inthis paper. Testing results indicate the designs of power supply module, clock moduleand reset module on the two boards meet the expected target, and the test systembasically meet the test of chip’s specifications.70%specifications of the testing chipembedded on the chip test backplane are tested completely on the multifunctional testboard. The tests contents four types timing tolerance tests of Media IndependentInterface, test of Serializer&Deserializer module, test of chip clock and the timingrelationship test between power and reset. The test system proposed in this paper issuitable for the test of other type network chips.