Architecture Of Design-For-Testability And Its Optimization For System-On-Chip

Design methodology for integrated circuits has developed to System-on-Chip (SoC) level with the advance of technology and demands for high performance and Time-to-Market. Testing is the key technique for SoC design. Test architecture and methodology for SoC is becoming the main research domain of Design-for-Testability (DFT) in the near future.This dissertation is working on the architecture, methodology and scheme of design-for-testability for SoC.The SoC design introduces new challenges for testing, including (1) the deliverable test information from IP provider to SoC integrator, (2) test access mechanism (TAM) of IP core under test, (3) test integration and optimization, (4) testing of mixed-signal IP core. IEEE P1500 standard for embedded core test is a standard-under-development that aims at improving the SoC testing. IEEE P1500 standard provides a basic framework for SoC testing, accepted by not only industry but also academe, for example, Virtual Socket Interface Alliance (VSIA) will follow the scheme of IEEE P1500. IEEE P1500 standardizes test wrapper and Core Test Language (CTL), and leaves the research and design of test access mechanism, test source and sink, testing integration, optimization, analog and mixed-signal testing to the IP provider, SoC integrator and EDA group. The dissertation will research on the test access and control mechanism based on IEEE P1500. The IEEE P1500 compliant wrapper has been designed. A test access mechanism and control architecture based on the test bus named TAM-Bus is presented. Then, the dissertation focuses on delivery issue of test information, i.e. the test pattern's translation for IP-core level to SoC level.The testing time decides the test cost for SoC. In order to reduce test cost, the testing time for a SoC should be minimized under limited test resource such as limited test width and test ports by optimizing the test architecture for embedded IP cores. The dissertation studied test wrapper and TAM co-optimization, presented an optimization scheme based on hybrid genetic algorithm to solve the wrapper optimization issue under constraints of width of TAM, and proposed optimization schemes based on niche genetic algorithm to solve the wrapper and TAM co-optimization issues such as TAM partition and subdivision. These schemes have better results and minimize the testing time for a SoC effectively.More and more analog and mixed-signal IP cores are integrated in SoC besides large numbers of digital IP cores. The dissertation explored the testing of these analog and mixed-signal IP cores and focused on the analog and mixed-signal test access mechanism for them in order to provide a scheme for testing of these cores. Because the IEEE P1500 has not covered the content of analog and mixed-signal IPs up to now, an analog and mixed-signal SoC test architecture extended from IEEE P1500 is proposed. The architecture not only provides the analog access mechanism to IPs, but also an IEEE P1500 compliant TAM to the digital portions of IPs.As most frequently integrated mixed-signal IP in SoC, analog to digital converter (ADC) brings more complex testing work. A built-in self-test (BIST) is an efficient technique for testing embedded ADC. Focusing on the built-in self-test (BIST) for ADC based on histogram,the dissertation proposed an on-chip ramp generator with digital calibrator for providing linear stimulus in BIST scheme by using digital ?Σnoise chapping technique, presented a parallel time decomposition and a fold linear histogram BIST schemes to achieve shorter testing time under low hardware overhead by improving time decomposition concept. The interface to TAM-Bus and JTAG, provided by the BIST in our scheme, can be integrated in SoC architecture more easily and the SoC test is simplified accordingly.Through the researches mentioned above, the test architecture, optimization method and test scheme are provided for SoC to reduce both difficulties and costs of SoC test.