Design Of Low-Voltage High-Speed ADC For Gigabit Ethernet

With the stepping into the digital era, there exists an increasing demand for data transmission rate by Ethernet. The 10Mbps and 100Mbps data transmission rate of the existing fast Ethernet can't meet the requirements of many applications. Therefore, IEEE started the design of transimission standards concerned Gigabit Ethernet very early in 1996 and released the Gigabit Ethernet transmission standards with fibre and CAT-5 unshielded twisted-pair cabling respectively in 1998 and 1999.In Gigabit Ethernet based on CAT-5 unshielded twisted-pair cabling, the analog front-end transceiver needs four 7 to 8-bit ADCs having a sampling rate of 125MHz to convert the received analog signal to digital data 8-bit ADCs with sampling rates above 100MHz can be found in portable digital oscilloscopes, too. Furthermore, high-speed moderate-resolution ADCs are required widely in applications such as LCD driver, radar, hard disk driver.As a bottleneck in the mixed-signal system design, high-speed ADC consumes a large chip area, power budget and designing period. Among a lot of ADC architectures, folding and interpolating technology possesses advantages of high speed, low power, small chip area, easiness to be compatible with digital process, etc. Most of the folding and interpolating ADCs were realized in bipolar process before the mid 90s. With the development of the CMOS process and design technique, more and more folding and interpolating ADCs are realized in CMOS technology now. The evolution for System-on-Chip (SoC) requires an ADC embedded i n a system chip. Though folding and interpolating ADC has a comparably small chip area, the reported research results show that nearly all occupy an area of about 1mm2 or above, which is not appropriate for embedded applications.Based on the above researchs, this dissertation focus on the design of an 8-bit 125-MSPS (also OK for 200-MSPS) small-area ADC used in Gigabit Ethernet. The main contri butions can be concluded as folIowi ng:(1) A novel transistor-only folder is designed. Compared with a conventional folder with resistive loads, the novel folder replaces the resistive loads completely with transistors. The transistor-only folder has a better power-supply rejection capability regarding the common-mode output voltage. Without using resistive loads, the common-mode output voltage and the gain of the proposed folder are insensitive to the process variations. The...