Implementation Of Onboard Image Compression System Using FPGA

In recent years,with the development of space exploration technology, resolu -tion of remote sensor is rapidly increasing, which helps to collect mass data and bring much difficulties to onboard storage and downlink transmission. To resolve the problem, high speed onboard image compression technology has been extensively developed. But there is still big disparity in the domain of onboard image compression technology between our country with advanced one. Consequently it is meaningful to research the design and implementation of practical onboard imagery compression system.The main research of the thesis is about the realization methods of onboard image compression on hardware. According to the requirements of space data system such as low power, high performance, flexibility and so on, the thesis uses FPGA as platform to implement algorithm based on CCSDS space data compression standard.The thesis firstly analyzes the advantages of CCSDS algorithm and selects FPGA as implementation platform through comparison. Secondly the thesis determines the encoding option that applies to the project through detailed analysis and targeted experiments. Thirdly the FPGA based overall architecture and architectures of functional modules such as wavelet transform, DC encoding and bit-plane encoding are separately designed. Then through performance analysis and simulation the resources occupation and the rate parameters are achieved, which validates the design. Finally the full prototype and verification system is physically implemented, which includes the FPGA based image compression card, USB card and image send/receive software on host computer, and through testing the system performance parameters are acquired.The contributions of the thesis can be summarized as follows:1. Proposing a kind of FPGA based architecture of CCSDS image compression algorithm. The algorithm is decomposed into function blocks and the relation between them is expounded, based on which the architecture is designed by parallel and pipeline methods.2. Proposing a kind of architecture of 9/7 integer wavelet transform which features by external memory saving. The structure is fit for block-based transform, and save transform coefficients in internal memory, which produces only a smaller delay. The artifact caused by blocking can be removed through the use of boundary lapped blocking measures.3. Proposing a kind of real-time two-dimensional wavelet transform hardware architecture that requires more out-of-chip memory, delays slightly larger, but occupies a smaller FPGA memory, be able to fully achieve real-time performance.4. Proposing a kind of bit-plane encoding architecture in pipeline and parallel methods. The architecture improves the original scan order, as significantly speed up the scan process. This structure can be adjusted for different rate requirements by properly change the parallelism degree.