FPGA Implementation Technologies Of Image Compression Algorithm On Board Satellite Based On CCSDS IDC

With the development of the aerospace technology, more and more remote sense image data are produced and the data transmission to ground becomes more and more difficult both in deep space probes and in the near earth observations, owing to the increasing resolution of the satellite imaging instruments. Therefore, the onboard image data compression plays an important role in the fields of deep space exploration and remote sense.At present, according to different techniques used for decorrelation, the image compression algorithms can be separated into DPCM, DCT and DWT-based in the onboard image compression systems. The main standards of still image compression include CCSDS LDC based on DPCM, JPEG based on DCT, and JPEG2000 and SPIHT based on DWT. But some of them have the disadvantages of high computational complexity, even block effect, which are not suitable for onboard satellite use. So the CCSDS starts to establish a new image data compression algorithm suitable for spaceborne applications, and the new image data compression recommendation standard called CCSDS Image Data Compression (IDC) Blue Book is finally published in November 2005. The IDC algorithm,9/7 DWT-based, supports both lossy and lossless compression and allows progressive transmission. The algorithm reduces computational complexity and the hardware implementation is fast and low power. CCSDS IDC achieves performance similar to JPEG2000. It is designed specially for space application, meeting the requirements of satellites.In order to compress the extensive amount of satellite image data in real time and solve the problem of data storage and transmission, the CCSDS IDC algorithm and its hardware implementation is researched in this paper. With the advanced FPGA technology and the new IDC algorithm, an IP soft core of IDC algorithm is designed and integrated into the PLB bus of the CoreConnect, aiming at building a single-chip satellite image compression system. The paper is summarized as follows:(1) Study on CCSDS IDC image data compression recommanded standard. The algorithm is analyzed and simulated in detail. The computational complexity and hardware implementation for IDC compression algorithm is lower than that of JPEG2000's. It is very suitable for the image data compression in satellite environment.(2) The 9/7 discrete wavelet transform algorithm is studied and it is converted into a lifting scheme, easy to calculate quickly and be implemented by VLSI.VLSI implementation architecture of 9/7 integer DWT lifting-based is proposed, which can simplify the computational procedure. VLSI implementation architecture of 9/7 float DWT convolution algorithm is also improved, and VLSI architecture of 9/7 float DWT lifting scheme is also designed. In the wavelet transform modules of convolution algorithm and lifting scheme, replacing constant coefficient multiplication operations, the shift-adder multipliers CSD-based get no multiplier computation, shorten the delay path, increase the computing frequency and save hardware resources.In the VLSI structure of two dimensional discrete wavelet transform, the parallel transformation of row and column structure speeds up the transformation and raises the efficiency of the wavelet transform. Row and column transformation modules use the embedded symmetric extension to reduce the required memory capacity.(3) The IDC's bit plane encoder is researched. Different from the DWT's intensive computation, its data operation is not complicated. It is a procedure mainly including a lot of comparison, shift and logical judgement operations. As a complex process, the data flow needs frequent access to the memory.VLSI implementation architecture of bit plane encoder based on parallel technique is proposed. The modules of initial coding of DC coefficient, AC coefficient bit depth coding and bit plane coding are designed.The parallel scan method based on set-type is used to reduce the scan time in a block. The parallel scan method based on block-group is used to shorten the scan time of a segment. And the parallel statistical method based on block-group is taken to speed up the optimal code option calculation for a bit plane. (4) A SoPC architecture of satellite image compression system is proposed, which is based on PowerPC processor. CoreConnect PLB bus and IDC IP soft core. The implementation of the single-chip image compression system aims to decrease the size, complexity and cost of the small satellite and shorten the development cycle. An IDC IP soft core based on CoreConnect PLB bus is designed and the IPIF interface in accordance to PLB bus is developed. An onboard image compression system composed of various IP core in a Xilinx Virtex-â…¡Pro FPGA is built.In this paper, on the basis of researching and designing the IDC's IP software core, the functional verification and system design are done. Finally, the system is verified and implemented in the Xilinx Virtex-â…¡Pro FPGA development system.